Patents by Inventor John M. Lauffer
John M. Lauffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6830875Abstract: A method for forming an electronic structure. Provides is a layer that includes a cylindrical volume of a photoimageable dielectric (PID) material, an annular volume of the PID material circumscribing the cylindrical volume, and a remaining volume of the PID material circumscribing the annular volume. The layer is photolithograhically exposed to radiation. The annular volume is fully cured by the radiation. The remaining volume is partially cured by the remaining volume by said radiation. The method prevents curing of the cylindrical volume, wherein the PID material in the cylindrical volume remains uncured.Type: GrantFiled: October 7, 2002Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Stephen J. Fuerniss, Gary Johansson, Ross W. Keesler, John M. Lauffer, Voya R. Markovich, Peter A. Moschak, David J. Russell, William E. Wilson
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Patent number: 6828514Abstract: A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.Type: GrantFiled: January 30, 2003Date of Patent: December 7, 2004Assignee: Endicott Interconnect Technologies, Inc.Inventors: Benson Chan, John M. Lauffer, How T. Lin, Voya R. Markovich, David L. Thomas
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Publication number: 20040231888Abstract: A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.Type: ApplicationFiled: March 30, 2004Publication date: November 25, 2004Applicant: Endicott Interconnect Technologies, Inc.Inventors: Benson Chan, John M. Lauffer, How T. Lin, Voya R. Markovich, David L. Thomas
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Patent number: 6815085Abstract: A capacitive element for a circuit board or chip carrier is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured followed by being fully cured. The partially cured sheet is laminated to at least one other sheet of dielectric material and one of the sheets of conductive material. The total thickness of the two sheets of the dielectric component does not exceed about 4 mils and preferably does not exceed about 3 mils. The use of two or more sheets of dielectric material makes it very unlikely that two or more defects in the sheets of dielectric material will align, thus greatly reducing the probability of a defect causing a failure in test or field use.Type: GrantFiled: May 12, 2003Date of Patent: November 9, 2004Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, John M. Lauffer
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Patent number: 6809269Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.Type: GrantFiled: December 19, 2002Date of Patent: October 26, 2004Assignee: Endicott Interconnect Technologies, Inc.Inventors: James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich
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Publication number: 20040177998Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.Type: ApplicationFiled: March 30, 2004Publication date: September 16, 2004Applicant: Endicott Interconnect Technologies, Inc.Inventors: James W. Fuller, John M. Lauffer, Voya R. Markovich
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Patent number: 6781064Abstract: A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package. This printed circuit board includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.Type: GrantFiled: June 29, 1999Date of Patent: August 24, 2004Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, Anilkumar C. Bhatt, James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich, William J. Rudik, William E. Wilson
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Publication number: 20040150969Abstract: A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.Type: ApplicationFiled: January 30, 2003Publication date: August 5, 2004Applicant: Endicott Interconnect Technologies Inc.Inventors: Benson Chan, John M. Lauffer, How T. Lin, Voya R. Markovich, David L. Thomas
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Publication number: 20040134685Abstract: A method of forming a printed circuit board with a metal power plane layer between two photoimageable dielectric layers is provided. Photoformed metal filled vias and plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials connected to the vias and plated through holes. A border may be around the board including a metal layer terminating in from the edge of one of the dielectric layers. Copper foil with clearance holes is provided. First and second layers of photoimageable curable dielectric material are on opposite sides of the copper. Patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. Through holes are developed where holes were patterned in both dielectric layers. The surfaces of the photoimageable material, vias and through holes are metallized by copper plating, preferably using photoresist.Type: ApplicationFiled: December 22, 2003Publication date: July 15, 2004Applicant: International Business Machines CorporationInventors: Kenneth Fallon, Miguel A. Jimarez, Ross W. Keesler, John M. Lauffer, Roy H. Magnuson, Voya R. Markovich, Irv Memis, Jim P. Paoletti, Marybeth Perrino, John A. Welsh, William E. Wilson
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Publication number: 20040118596Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.Type: ApplicationFiled: December 19, 2002Publication date: June 24, 2004Applicant: Endicott Interconnect Technologies, Inc.Inventors: James W. Fuller, John M. Lauffer, Voya R. Markovich
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Publication number: 20040118598Abstract: An information handling system (e.g., computer, server, etc.) Utilizing at least one circuitized substrate assembly of robust construction and possessing enhanced operational capabilities. The substrate assemblies include a substrate having at least one opening which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.Type: ApplicationFiled: March 6, 2003Publication date: June 24, 2004Applicant: Endicott Interconnect Technologies, Inc.Inventors: James W. Fuller, John M. Lauffer, Voya R. Markovich
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Patent number: 6750405Abstract: A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers.Type: GrantFiled: October 17, 2000Date of Patent: June 15, 2004Assignee: International Business Machines CorporationInventors: Kenneth Fallon, Miguel A. Jimarez, Ross W. Keesler, John M. Lauffer, Roy H. Magnuson, Voya R. Markovich, Irv Memis, Jim P. Paoletti, Marybeth Perrino, John A. Welsh, William E. Wilson
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Patent number: 6740819Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.Type: GrantFiled: April 23, 2003Date of Patent: May 25, 2004Assignee: International Business Machines CorporationInventors: Anilkumar C. Bhatt, Ashwinkumar C. Bhatt, Subahu D. Desai, John M. Lauffer, Voya R. Markovich, Thomas R. Miller
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Patent number: 6739046Abstract: A method is provided for connecting two conductive surfaces in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive surface, applying a dielectric insulation material over the first conductive surface such that the dendrites are exposed through the insulation material to leave a substantially planar surface of exposed dendrites, and placing a second conductive surface on top of the exposed dendrites. The second conductive surface may be a surface metal, a chip bump array, or a ball grid array. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection and planarization manufactured in accordance with the present invention.Type: GrantFiled: May 22, 2000Date of Patent: May 25, 2004Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, Saswati Datta, Michael A. Gaynes, John M. Lauffer, James R. Wilcox
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Patent number: 6739027Abstract: A method is provided for producing a capacitor to be embedded in an electronic circuit package comprising the steps of selecting a first conductor foil, selecting a dielectric material, coating the dielectric material on at least one side of the first conductor foil, and layering the coated foil with a second conductor foil on top of the coating of dielectric material. Also claimed is an electronic circuit package incorporating at least one embedded capacitor manufactured in accordance with the present invention.Type: GrantFiled: April 20, 2000Date of Patent: May 25, 2004Assignee: International Business Machines CorporationInventors: John M. Lauffer, Konstantinos Papathomas
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Patent number: 6700078Abstract: A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.Type: GrantFiled: June 19, 2002Date of Patent: March 2, 2004Assignee: International Business Machines CorporationInventors: Donald S. Farquhar, Robert M. Japp, John M. Lauffer, Konstantinos I. Papathomas
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Patent number: 6689543Abstract: An epoxy based resin which exhibits good laser ablation and good adherence to a substrate such a copper is provided by adding to the resin a dye or dyes having substantial energy absorption at the emission wave lengths of lasers used to laser ablate the resin. The resin with the dye or dyes included is coated onto a substrate and cured, or laminated onto a substrate in the cured condition. The required openings are formed in the cured film by laser ablation. This allows for the use of optimum techniques to be used to form micro vias.Type: GrantFiled: February 11, 2002Date of Patent: February 10, 2004Assignee: International Business Machines CorporationInventors: John S. Kresge, John M. Lauffer, David J. Russell
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Publication number: 20030202314Abstract: A capacitive element for a circuit board or chip carrier is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured followed by being fully cured. The partially cured sheet is laminated to at least one other sheet of dielectric material and one of the sheets of conductive material. The total thickness of the two sheets of the dielectric component does not exceed about 4 mils and preferably does not exceed about 3 mils. The use of two or more sheets of dielectric material makes it very unlikely that two or more defects in the sheets of dielectric material will align, thus greatly reducing the probability of a defect causing a failure in test or field use.Type: ApplicationFiled: May 12, 2003Publication date: October 30, 2003Applicant: International Business Machines CorporationInventors: Bernd K., Appelt, John M. Lauffer
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Publication number: 20030188890Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.Type: ApplicationFiled: April 23, 2003Publication date: October 9, 2003Applicant: IBM CorporationInventors: Anilkumar C. Bhatt, Ashwinkumar C. Bhatt, Subahu D. Desai, John M. Lauffer, Voya R. Markovich, Thomas R. Miller
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Patent number: 6625857Abstract: A method of forming a capacitive element for a circuit board or chip carrier having improved capacitance is provided. The element is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured followed by being fully cured. The lamination takes place by laminating a partially cured sheet to at least one other sheet of dielectric material and one of the conductive sheets. The total thickness of the two sheets of the dielectric component does not exceed about 4 rolls and preferably does not exceed about 3 mils; thus, the single dielectric sheet does not exceed about 2 mils and preferably does not exceed about 1.5 mils in thickness.Type: GrantFiled: February 1, 2001Date of Patent: September 30, 2003Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, John M. Lauffer