Patents by Inventor John M. Lauffer

John M. Lauffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7838776
    Abstract: A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: November 23, 2010
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: John M. Lauffer, Voya R. Markovich, Michael Wozniak
  • Patent number: 7827682
    Abstract: Apparatus and method for making circuitized substrates using a continuous roll format in which a layer of conductor is fed into the apparatus, layers of photo-imageable dielectric are applied to opposite sides of the conductor layer, thru-holes are formed through the composite, and then metal layers are added over the dielectric and then patterns (e.g., circuit) are formed therein. Several operations are performed in addition to these to form the final end product, a circuitized substrate (e.g., printed circuit board), all while the conductor layer of the product is retained in a solid format, up to the final separation from the continuous layer.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: November 9, 2010
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: John M. Lauffer, Voya R. Markovich, James J. McNamara, Jr., Peter A. Moschak
  • Patent number: 7814649
    Abstract: A method of making a circuitized substrate which includes a plurality of contiguous open segments along a side edge portion of the at least one electrically conductive layer thereof, these open segments isolated by a barrier of dielectric material which substantially fills the open segments, e.g., during a lamination process which bonds two dielectric layers of the substrate to the conductive layer.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: October 19, 2010
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: John M. Lauffer, James M. Larnerd, Voya R. Markovich
  • Patent number: 7803688
    Abstract: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: September 28, 2010
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, Frank D. Egitto, John M. Lauffer, How T. Lin, Voya R. Markovich
  • Patent number: 7800916
    Abstract: A circuitized substrate assembly comprised of at least two circuitized substrates each including a thin dielectric layer and a conductive layer with a plurality of conductive members as part thereof, the conductive members of each substrate being electrically coupled to the conductive sites of a semiconductor chip. A dielectric layer is positioned between both substrates and the substrates are bonded together, such that the chips are internally located within the assembly and oriented in a stacked orientation. A method of making such an assembly is also provided, as is an electrical assembly utilizing same and an information handling system adapted for having such an electrical assembly as part thereof.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: September 21, 2010
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Kim J. Blackwell, Frank D. Egitto, John M. Lauffer, Voya R. Markovich
  • Patent number: 7791897
    Abstract: A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: September 7, 2010
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, John M. Lauffer, Irving Memis, Steven G. Rosser
  • Publication number: 20100167210
    Abstract: A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.
    Type: Application
    Filed: March 10, 2010
    Publication date: July 1, 2010
    Applicant: ENDICOTT INTERCONNECT TECHNOLOGIES, INC.
    Inventors: Rabindra N. Das, John M. Lauffer, Irving Memis, Steven G. Rosser
  • Publication number: 20100060381
    Abstract: A multi-layer imbedded capacitance and resistance substrate core. At least one layer of resistance material is provided. The layer of resistance material has a layer of electrically conductive material embedded therein. At least one layer of capacitance material of high dielectric constant is disposed on the layer of resistance material. Thru-holes are formed by laser.
    Type: Application
    Filed: September 9, 2008
    Publication date: March 11, 2010
    Inventors: Rabindra N. Das, John M. Lauffer, Irving Memis, Steven G. Rosser
  • Patent number: 7627947
    Abstract: A method of making a multilayered circuitized substrate in which a continuous process is used to form electrically conductive layers which each will form part of a sub-composite. The sub-composites are then aligned such that openings within the conductive layers are also aligned, the sub-composites are then bonded together, and a plurality of holes are then laser drilled through the entire thickness of the bonded structure. The dielectric layers used in the sub-composites do not include continuous or semi-continuous fibers therein, thus expediting hole formation there-through.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: December 8, 2009
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Thomas J. Davis, Subahu D. Desai, John M. Lauffer, James J. McNamara, Jr., Voya R. Markovich
  • Patent number: 7629559
    Abstract: A method of improving conductive paste connections in a circuitized substrate in which at least one and preferably a series of high voltage pulses are applied across the paste and at least one and preferably a series of high current pulses are applied, both series of pulses applied separately. The result is an increase in the number of conductive paths through the paste connections from those present prior to the pulse applications and a corresponding resistance reduction in said connections.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: December 8, 2009
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Subahu D. Desai, John M. Lauffer, How T. Lin, Voya R. Markovich, Ronald V. Smith
  • Publication number: 20090241332
    Abstract: A circuitized substrate and method of making same in which a first plurality of holes are formed within two bonded dielectric layers and then made conductive, e.g., plated. The substrate also includes third and fourth dielectric layers bonded to the first and second with a plurality of continuous electrically conductive thru holes extending through all four dielectric layers. Conductive paste is positioned within the thru holes for providing electrical connections between desired conductive layers of the substrate and outer layers as well. A circuitized substrate assembly and method of making same are also provided.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Inventors: John M. Lauffer, Roy H. Magnuson, Voya R. Markovich, James P. Paoletti, Kostas I. Papathomas, Rajinder S. Rai
  • Publication number: 20090206051
    Abstract: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.
    Type: Application
    Filed: March 2, 2009
    Publication date: August 20, 2009
    Inventors: Rabindra N. Das, Frank D. Egitto, John M. Lauffer, How T. Lin, Voya R. Markovich
  • Publication number: 20090178273
    Abstract: A method of forming a circuitized substrate assembly in which at least two adjacent and contiguous circuitized substrates have at least one, and possibly a second, circuitized substrate positioned thereon and bonded thereto to form a combined circuitized substrate assembly. The substrates each include at least one conductive thru-hole therein such that the bonding will cause respective pairs (at least one pair if only three substrates are used) of the thru-holes to align and become electrically coupled, thereby forming at least one and preferably more electrical circuit paths through the combined assembly to electrically couple electrical components positioned on selected ones of the circuitized substrates.
    Type: Application
    Filed: January 15, 2008
    Publication date: July 16, 2009
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventor: John M. Lauffer
  • Publication number: 20090178271
    Abstract: A method of making a circuitized substrate which involves forming a plurality of individual film resistors having approximate resistance values as part of at least one circuit of the substrate, measuring the resistance of a representative (sample) resistor to define its resistance, utilizing these measurements to determine the corresponding precise width of other, remaining film resistors located in a defined proximity relative to the representative resistor such that these remaining film resistors will include a defined resistance value, and then selectively isolating defined portions of the resistive material of these remaining film resistors while simultaneously defining the precise width of the resistive material in order that these film resistors will possess the defined resistance.
    Type: Application
    Filed: January 16, 2008
    Publication date: July 16, 2009
    Applicant: Endicott Interconnect Technologies, Inc.
    Inventors: Frank D. Egitto, John S. Kresge, John M. Lauffer
  • Patent number: 7541265
    Abstract: A material for use as part of an internal capacitor within a circuitized substrate includes a polymer (e.g., a cycloaliphatic epoxy or phenoxy based) resin and a quantity of nano-powders of ferroelectric ceramic material (e.g., barium titanate) having a particle size substantially in the range of from about 0.01 microns to about 0.90 microns and a surface area for selected ones of said particles within the range of from about 2.0 to about 20 square meters per gram. A circuitized substrate adapted for using such a material and capacitor therein and a method of making such a substrate are also provided. An electrical assembly (substrate and at least one electrical component) and an information handling system (e.g., personal computer) are also provided.
    Type: Grant
    Filed: January 10, 2005
    Date of Patent: June 2, 2009
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Rabindra N. Das, John M. Lauffer, Kostas I. Papathomas, Mark D. Poliks
  • Patent number: 7530167
    Abstract: A method of making a printed circuit board in which the board includes a common power plane having dielectric layers on opposing sides thereof and a signal layer on each of said dielectric layers, each signal layer comprising a plurality of substantially parallel signal lines running in substantially similar directions across said signal layers. Predetermined portions of the signal lines in one signal layer are aligned relative to and also parallel to corresponding signal lines in the other signal layer, with the power plane being located between these portions. Through hole connections are provided between selected signal lines in the two layers, these occurring through clearance holes in the power plane so as to be isolated therefrom.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: May 12, 2009
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: John M. Lauffer, Voya R. Markovich, James J. McNamara, Jr., David L. Thomas
  • Patent number: 7491896
    Abstract: An information handling system, e.g., a mainframe computer, which includes as part thereof a housing having therein an electrical assembly including a circuitized substrate which in turn includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within the system. At least one electrical component is positioned on and electrically coupled to the circuitized substrate of the system's electrical assembly.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: February 17, 2009
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: John M. Lauffer, James M. Larnerd, Voya R. Markovich
  • Patent number: 7478472
    Abstract: A method of making a circuitized substrate in which at least one signal line used therein is shielded by a pair of opposingly positioned ground lines which in turn are electrically coupled to a ground plane located beneath the signal and ground lines and separated therefrom by a common interim dielectric layer. The substrate may form part of a larger structure such as a PCB, chip carrier or the like.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: January 20, 2009
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: John M. Lauffer, Voya Markovich, Corey Seastrand, David L. Thomas
  • Patent number: 7449381
    Abstract: A method of forming a capacitive substrate in which at least one capacitive dielectric layer of material is screen or ink jet printed onto a conductor and the substrate is thereafter processed further, including the addition of thru-holes to couple selected elements within the substrate to form at least two capacitors as internal elements of the substrate. The capacitive substrate may be incorporated within a larger circuitized substrate, e.g., to form an electrical assembly. A method of making an information handling system including such substrates is also provided.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: November 11, 2008
    Assignee: Endicott Interconect Technologies, Inc.
    Inventors: Rabindra N. Das, John M. Lauffer, How T. Lin, Voya R. Markovich
  • Patent number: 7442879
    Abstract: A circuitized substrate which includes a conductive paste for providing electrical connections. The paste, in one embodiment, includes a binder component and at least one metallic component including microparticles. In another embodiment, the paste includes the binder and a plurality of nano-wires. Selected ones of the microparticles or nano-wires include a layer of solder thereon. A method of making such a substrate is also provided, as are an electrical assembly and information handling system adapter for having such a substrate as part thereof.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: October 28, 2008
    Assignee: Endicott Interconect Technologies, Inc.
    Inventors: Rabindra N. Das, John M. Lauffer, Roy H. Magnuson, Voya R. Markovich