Patents by Inventor Joseph Fjelstad

Joseph Fjelstad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7528008
    Abstract: A method of electrically connecting a microelectronic component having a first surface bearing a plurality of contacts. The method including the steps of forming a subassembly by juxtaposing a connection component having a support structure and a plurality of elongated posts extending substantially parallel to one another from a first surface of the support structure with the microelectronic component so that the support structure overlies the surface of the component with the posts extending away from the component and electrically connecting the posts to the contacts of the microelectronic component.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: May 5, 2009
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Patent number: 7408260
    Abstract: A microelectronic assembly includes a microelectronic element such as a semiconductor chip or wafer having a first surface and contacts accessible at the first surface, a compliant layer overlying the first surface of the microelectronic element, and conductive protrusions overlying the compliant layer and projecting away from the first surface of the microelectronic element, wherein the conductive protrusions are electrically interconnected with the contacts of the microelectronic element. The conductive protrusions are movable relative to said microelectronic element.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: August 5, 2008
    Assignee: Tessera, Inc.
    Inventors: Joseph Fjelstad, Konstantine Karavakis
  • Publication number: 20070236901
    Abstract: A signal-segregating connector for use in a system having a printed circuit board, a first electrical structure and a second electrical structure. The connector includes a first set of conductive elements to convey signals between the first electrical structure and the printed circuit board, and a second set of conductive elements to convey signals between the first electrical structure and the second electrical structure.
    Type: Application
    Filed: May 14, 2007
    Publication date: October 11, 2007
    Inventors: Kevin Grundy, Gary Yasumura, Joseph Fjelstad, William Wiedemann, Para Segaram
  • Patent number: 7276400
    Abstract: A method of making a microelectronic assembly includes providing a first microelectronic element having a first surface and a plurality of contacts exposed at the first surface; providing a second microelectronic element having a top surface and a plurality of contacts exposed at the top surface, forming a plurality of conductive elastomeric posts that connect at least some of the contacts of the first microelectronic element to at least some of the contacts of the second microelectronic element, and injecting a compliant material between the first surface of the first microelectronic element and the top surface of the second microelectronic element to form a compliant layer.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: October 2, 2007
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Publication number: 20070178774
    Abstract: An electrical interconnection device for establishing redundant contacts between the ends of two conductive elements to be mated, creating a electrical interconnection without capacitive stubs.
    Type: Application
    Filed: December 1, 2006
    Publication date: August 2, 2007
    Inventors: Gary Yasumura, Joseph Fjelstad, Kevin Grundy, William Wiedemann, Matthew Stepovich
  • Publication number: 20070066046
    Abstract: A method of electrically connecting a microelectronic component having a first surface bearing a plurality of contacts. The method including the steps of forming a subassembly by juxtaposing a connection component having a support structure and a plurality of elongated posts extending substantially parallel to one another from a first surface of the support structure with the microelectronic component so that the support structure overlies the surface of the component with the posts extending away from the component and electrically connecting the posts to the contacts of the microelectronic component.
    Type: Application
    Filed: November 20, 2006
    Publication date: March 22, 2007
    Applicant: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Publication number: 20070046889
    Abstract: An eyewear assembly having flexible temple elements with counterweights is disclosed. The counterweights and flexible temples can serve several other purposes aside from the disclosed role of supporting eyewear on a wearer's face. Those purposes include ornamental elegance in design and facilitating a natural adjustability around unique personal features for position and comfort. The flexible temple elements provide mechanisms for transmitting electrical, mechanical and photonic power and or signals to the eyewear while the counterweights provide the source for said transmissions from a more convenient location.
    Type: Application
    Filed: August 23, 2006
    Publication date: March 1, 2007
    Inventors: Kenneth Miller, Michael Fjelstad, Joseph Fjelstad
  • Patent number: 7176580
    Abstract: Disclosed are structures and methods that facilitate the use of wire bonding technology over active areas of an IC chip. The invention is also suitable for use with IC structures that use brittle dielectric materials such as low K dielectrics.
    Type: Grant
    Filed: October 25, 2004
    Date of Patent: February 13, 2007
    Inventor: Joseph Fjelstad
  • Patent number: 7165316
    Abstract: An electrical resistor is made by providing a sacrificial layer and conductive pads disposed on a first surface of the sacrificial layer. An electrically resistive material is deposited over the pads and on the first surface of the sacrificial layer to form at least one unit including the resistive material and the pads. At least part of the sacrificial layer is then removed so as to expose one or more of the pads.
    Type: Grant
    Filed: April 20, 2004
    Date of Patent: January 23, 2007
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Publication number: 20060261476
    Abstract: A microelectronic assembly includes a microelectronic element such as a semiconductor chip or wafer having a first surface and contacts accessible at the first surface, a compliant layer overlying the first surface of the microelectronic element, and conductive protrusions overlying the compliant layer and projecting away from the first surface of the microelectronic element, wherein the conductive protrusions are electrically interconnected with the contacts of the microelectronic element. The conductive protrusions are movable relative to said microelectronic element.
    Type: Application
    Filed: July 14, 2006
    Publication date: November 23, 2006
    Applicant: Tessera, Inc.
    Inventors: Joseph Fjelstad, Konstantine Karavakis
  • Patent number: 7138299
    Abstract: A method of electrically connecting a microelectronic component having a first surface bearing a plurality of contacts. The method including the steps of forming a subassembly by juxtaposing a connection component having a support structure and a plurality of elongated posts extending substantially parallel to one another from a first surface of the support structure with the microelectronic component so that the support structure overlies the surface of the component with the posts extending away from the component and electrically connecting the posts to the contacts of the microelectronic component.
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: November 21, 2006
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Publication number: 20060244150
    Abstract: Disclosed are IC package structures having stair stepped layers and which have no plated vias. Such structures can be fabricated either as discrete packages or as strips such as might be beneficial in for use with memory devices wherein critical or high speed signals can be routed along the length of the multi-chip strip package without having to have the signals ascend and descend from the interconnection substrate on which the assembly is mounted to the IC package termination and back as the signal transmits between devices.
    Type: Application
    Filed: May 2, 2006
    Publication date: November 2, 2006
    Inventor: Joseph Fjelstad
  • Publication number: 20060237836
    Abstract: A compliant semiconductor chip package assembly includes a a semiconductor chip having a plurality of chip contacts, and a compliant layer having a top surface, a bottom surface and sloping peripheral edges, whereby the bottom surface of the compliant layer overlies a surface of the semiconductor chip. The assembly also includes a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, the traces extending along the sloping edges to the top surface of the compliant layer. The assembly may include conductive terminals overlying the semiconductor chip, with the compliant layer supporting the conductive terminals over the semiconductor chip. The conductive traces have first ends electrically connected with the contacts of the semiconductor chip and second ends electrically connected with the conductive terminals. The conductive terminals are movable relative to the semiconductor chip.
    Type: Application
    Filed: June 23, 2006
    Publication date: October 26, 2006
    Applicant: Tessera, Inc.
    Inventors: Joseph Fjelstad, Konstantine Karavakis
  • Patent number: 7112879
    Abstract: A microelectronic package includes a microelectronic element having contacts accessible at a surface thereof, a layer overlying the microelectronic element, the layer having a first surface and a sloping peripheral edge extending away from the first surface of the layer, and conductive terminals overlying the microelectronic element, wherein the layer supports the conductive terminals over the microelectronic element. The package also includes conductive traces having first ends electrically connected with the contacts of the microelectronic element and second ends electrically connected with the conductive terminals, with at least one of the conductive traces having a section that is in contact with and extends along the sloping peripheral edge of the layer, and a compliant material disposed between the conductive terminals and the microelectronic element so that the conductive terminals are movable relative to the microelectronic element.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: September 26, 2006
    Assignee: Tessera, Inc.
    Inventors: Joseph Fjelstad, Konstantine Karavakis
  • Patent number: 7095054
    Abstract: A microelectronic package includes a light sensitive microelectronic element having a front face including one or more contacts and a rear surface, and conductive leads having first ends connected to the one or more contacts and second ends connected to one or more conductive pads adjacent the light sensitive microelectronic element. The package also includes an at least partially transparent encapsulant covering the light sensitive microelectronic element, the conductive leads and the one or more conductive pads, whereby the one or more conductive pads are exposed on a surface of the encapsulant.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: August 22, 2006
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Patent number: 7091820
    Abstract: A microelectronic assembly, including a microelectronic element such as a semiconductor chip and a dielectric material covering the chip and forming a body having a bottom surface. The assembly includes conductive units having portions exposed at the bottom surface, posts extending upwardly from said exposed portions and top flanges spaced above the bottom surface.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: August 15, 2006
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Publication number: 20060157846
    Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.
    Type: Application
    Filed: February 13, 2006
    Publication date: July 20, 2006
    Inventors: Joseph Fjelstad, Para Segaram, Thomas Obenhuber, Kevin Grundy, Inessa Obenhuber
  • Patent number: 7067742
    Abstract: A connection component for use in making microelectronic element assemblies which has peelable leads that are formed on a dielectric support structure. One end of each lead is permanently connected to the support structure and the opposite end of the lead is releasably connected to the support structure. When the releasable end of the lead is bonded to a contact on a semiconductor chip, the releasable end of the lead can be peeled from the support structure such that the chip may be moved away from the support structure. A compliant layer may be disposed between the chip and the support structure. If a compliant material is injected between the chip and the support structure to form the compliant layer, the compliant material will lift the chip away from the support structure and facilitate the peeling of the leads from the support structure.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: June 27, 2006
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Joseph Fjelstad, Belgacem Haba, Owais Jamil, Konstantine Karavakis, David Light, John W. Smith
  • Patent number: 7049929
    Abstract: Circuit panels are provided with resistors in vias extending between the top and bottom surfaces of the panels. The resistors may be formed by depositing a composite in each via, as by depositing a dispersion of a conductive material and a dielectric or by depositing one or more thin layers of a conductor. The resistors may be disposed at interior locations buried within a multilayer circuit board formed by laminating one or more panels having such resistors with one or more additional elements.
    Type: Grant
    Filed: May 1, 2002
    Date of Patent: May 23, 2006
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Publication number: 20060091507
    Abstract: Disclosed are IC package structures comprised of standard IC packages modified with separate circuit interconnection structures and disposed to interconnect either directly to other IC packages or to intermediate pedestal connectors which serve to support and interconnect various circuit elements, thus effectively allowing critical signals to bypass the generally less capable interconnection paths within standard interconnection substrates.
    Type: Application
    Filed: July 14, 2005
    Publication date: May 4, 2006
    Inventors: Joseph Fjelstad, Kevin Grundy, Gary Yasumura