Patents by Inventor Joseph Fjelstad

Joseph Fjelstad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6885106
    Abstract: A stacked microelectronic assembly includes a dielectric element and a first and second microelectronic element stacked one atop the other with the first microelectronic element disposed between the second microelectronic element and the dielectric. The dielectric element has opposed first and second surfaces with conductive features exposed at the first surface and terminals exposed on the second surface. Preferably, the contact-bearing face of the first microelectronic element confronts the first surface of the dielectric with at least some of the conductive features being movable with respect to the contacts or terminals. By providing such movable features, joining units have heights of about 300 microns or less may be joined to the terminals thereby reducing the overall height of the microelectronic assembly to 1.2 mm and less.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: April 26, 2005
    Assignee: Tessera, Inc.
    Inventors: Philip Damberg, Craig S. Mitchell, John B. Riley, Michael Warner, Joseph Fjelstad
  • Publication number: 20050085012
    Abstract: A method of electrically connecting a microelectronic component having a first surface bearing a plurality of contacts. The method including the steps of forming a subassembly by juxtaposing a connection component having a support structure and a plurality of elongated posts extending substantially parallel to one another from a first surface of the support structure with the microelectronic component so that the support structure overlies the surface of the component with the posts extending away from the component and electrically connecting the posts to the contacts of the microelectronic component.
    Type: Application
    Filed: November 3, 2004
    Publication date: April 21, 2005
    Applicant: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Patent number: 6876212
    Abstract: A probe card for testing an electrical element such as a semiconductor wafer or a printed wiring board includes a substrate with circuitry thereon, an encapsulant layer overlying the substrate and a multiplicity of leads extending upwardly from the substrate through the encapsulant layer to terminals, the terminals projecting above the encapsulant layer. The probe card can be engaged with the electronic element so that the tips of the leads bear on the contact pads of the electronic element, and so that the leads and encapsulant layer deform to accommodate irregularities in the electronic element or probe card. The card can be made by providing the substrate, a sacrificial layer and leads extending between the sacrificial layer and substrate, moving the substrate and sacrificial layer away from one another to deform the leads and injecting a curable material around the leads to form the encapsulant layer.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: April 5, 2005
    Assignee: Tesseva, Inc.
    Inventor: Joseph Fjelstad
  • Publication number: 20050035357
    Abstract: A microelectronic package includes a light sensitive microelectronic element having a front face including one or more contacts and a rear surface, and conductive leads having first ends connected to the one or more contacts and second ends connected to one or more conductive pads adjacent the light sensitive microelectronic element. The package also includes an at least partially transparent encapsulant covering the light sensitive microelectronic element, the conductive leads and the one or more conductive pads, whereby the one or more conductive pads are exposed on a surface of the encapsulant.
    Type: Application
    Filed: September 24, 2004
    Publication date: February 17, 2005
    Applicant: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Patent number: 6856235
    Abstract: A method of making resistors includes providing a sacrificial layer. Conductive material is then formed over a region of the sacrificial layer. Resistive material is then deposited over the first surface of the sacrificial layer such that the resistive material covers the sacrificial layer and the conductive material. A portion of the sacrificial layer is then removed to expose the conductive material. A method of making resistors includes the steps of providing a sacrificial layer, removing at least a portion of the sacrificial layer from regions of the sacrificial layer so as to create a plurality of cavities within the sacrificial layer, plating said cavities with a conductive material, disposing resistive material over the first surface of the sacrificial layer such that resistive material covers the sacrificial layer and said conductive material, and removing at least a portion of said sacrificial layer to expose the conductive material.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: February 15, 2005
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Patent number: 6848173
    Abstract: A method of making a microelectronic assembly includes juxtaposing a first element, such as a dielectric sheet having conductive leads thereon with a second element, such as a semiconductor chip, having contact thereon, and wire bonding the conductive leads on the first element to the contacts on the second element so that elongated bonding wires extend between the conductive leads and the contacts. After the wire bonding step, the first and second elements are moved through a pre-selected displacement relative to one another so as to deform the bonding wires. A flowable dielectric material may be introduced between the first and second elements and around the bonding wires during or after the moving step. The flowable material may be cured to form an encapsulant around at least a portion of the bonding wires.
    Type: Grant
    Filed: January 22, 2001
    Date of Patent: February 1, 2005
    Assignee: Tessera, Inc.
    Inventors: Joseph Fjelstad, Masud Beroz, John W. Smith, Belgacem Haba
  • Patent number: 6847107
    Abstract: By causing the movement of charge from a toner to a latent image carrier, the amount of charge of the toner is lowered to an amount of charge suitable for facilitating the transfer of toner so as to improve the transfer efficiency. For this, an image forming apparatus includes a latent image carrier and a developing means for forming a negatively chargeable toner layer composed of two stories or less on a toner carrier by a toner layer thickness regulating member. An electrostatic latent image on the latent image carrier is developed with the toner to form a visible image and the visible image is transferred to a transfer medium. Further, the work function (?opc) of the surface of the latent image carrier is set to be larger than the work function (?t) of the toner.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: January 25, 2005
    Assignee: Tessera, Inc.
    Inventors: Joseph Fjelstad, Konstantine Karavakis
  • Patent number: 6847101
    Abstract: A microelectronic assembly includes a microelectronic element having a first surface with a plurality of contacts accessible at the first surface, and a compliant layer over the first surface of the microelectronic element, the compliant layer including a plurality of bumped protrusions and openings adjacent the bumped protrusions for providing access to the contacts, wherein each bumped protrusion includes a top surface and at least one sloping edge. The microelectronic assembly also includes conductive terminals over the top surfaces of the bumped protrusions, and a plurality of conductive bond ribbons having first ends in engagement with the contacts, second ends in engagement with the terminals and intermediate sections extending along the sloping edges for electrically interconnecting the contacts and the terminals.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: January 25, 2005
    Assignee: Tessera, Inc.
    Inventors: Joseph Fjelstad, Konstantine Karavakis
  • Publication number: 20050014395
    Abstract: A device module may be used to carry a plurality of devices, such as memory devices or other components. The device module may include a board, a first set of contact points, and a second set of contact points. A plurality of signal paths may be provided on the board, where each signal path extends between a contact point in the first set and a contact point in the second set. Each of the plurality of signal paths has substantially an identical length and a same number of turns on the board.
    Type: Application
    Filed: January 13, 2004
    Publication date: January 20, 2005
    Inventors: Joseph Fjelstad, Para Segaram, Thomas Obenhuber, Gary Yasumura
  • Publication number: 20040233035
    Abstract: A microelectronic assembly, including a microelectronic element such as a semiconductor chip and a dielectric material covering the chip and forming a body having a bottom surface. The assembly includes conductive units having portions exposed at the bottom surface, posts extending upwardly from said exposed portions and top flanges spaced above the bottom surface.
    Type: Application
    Filed: June 30, 2004
    Publication date: November 25, 2004
    Applicant: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Patent number: 6821815
    Abstract: A method of encapsulating a microelectronic assembly comprises providing a microelectronic assembly having an element defining exterior surfaces and an array of terminals exposed at the exterior surfaces. The element defines an aperture through the exterior surfaces. A layer of a curable barrier material is screen printed onto a supporting element. The supporting element is assembled with the microelectronic assembly so that the layer of curable barrier material contacts the exterior surfaces and covers said one or more apertures. An encapsulant is applied to the microelectronic assembly.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: November 23, 2004
    Assignee: Tessera, Inc.
    Inventors: John W. Smith, Joseph Fjelstad
  • Patent number: 6821821
    Abstract: An electrical resistor is made by providing a sacrificial layer and conductive pads disposed on a first surface of the sacrificial layer. An electrically resistive material is deposited over the pads and on the first surface of the sacrificial layer to form at least one unit including the resistive material and the pads. At least part of the sacrificial layer is then removed so as to expose one or more of the pads.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: November 23, 2004
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Publication number: 20040227225
    Abstract: A microelectronic package includes a microelectronic element having contacts accessible at a surface thereof, a layer overlying the microelectronic element, the layer having a first surface and a sloping peripheral edge extending away from the first surface of the layer, and conductive terminals overlying the microelectronic element, wherein the layer supports the conductive terminals over the microelectronic element. The package also includes conductive traces having first ends electrically connected with the contacts of the microelectronic element and second ends electrically connected with the conductive terminals, with at least one of the conductive traces having a section that is in contact with and extends along the sloping peripheral edge of the layer, and a compliant material disposed between the conductive terminals and the microelectronic element so that the conductive terminals are movable relative to the microelectronic element.
    Type: Application
    Filed: June 22, 2004
    Publication date: November 18, 2004
    Applicant: Tessera, Inc.
    Inventors: Joseph Fjelstad, Konstantine Karavakis
  • Publication number: 20040194294
    Abstract: An electrical resistor is made by providing a sacrificial layer and conductive pads disposed on a first surface of the sacrificial layer. An electrically resistive material is deposited over the pads and on the first surface of the sacrificial layer to form at least one unit including the resistive material and the pads. At least part of the sacrificial layer is then removed so as to expose one or more of the pads.
    Type: Application
    Filed: April 20, 2004
    Publication date: October 7, 2004
    Applicant: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Publication number: 20040169263
    Abstract: An assembly including a first microelectronic element having a first surface and a plurality of contacts exposed at the first surface; a second microelectronic element having a top surface and a plurality of contacts exposed at the top surface; and conductive elastomeric posts formed by curing a conductive elastomeric material, wherein each of the contacts of the first microelectronic element is respectively aligned with one of the contacts of the second microelectronic element, and further wherein at least some of the contacts of the first element are connected to the respectively aligned contacts of the second element by the conductive elastomeric material.
    Type: Application
    Filed: August 19, 2003
    Publication date: September 2, 2004
    Applicant: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Patent number: 6780747
    Abstract: A method of providing a substantially void free layer for one or more flip chip assemblies, or one or more microelectronic components, utilizing a curable encapsulant. Also disclosed is a method of injecting an encapsulant into an assembly and a method of treating a microelectronic component to form a void free layer.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: August 24, 2004
    Assignee: Tessera, Inc.
    Inventors: Thomas H. Distefano, Joseph Fjelstad
  • Patent number: 6737265
    Abstract: Releasable leads having an elongated fixed portion extend over a surface defined by a dielectric material of a component or by a semiconductor body. A semiconductor element having a conductive structure connected to a set of contacts is also disclosed. A method of making the conductive structure is disclosed.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: May 18, 2004
    Assignee: Tessera, Inc.
    Inventors: Masud Beroz, Joseph Fjelstad, Belgacem Haba, Christopher M. Pickett, John Smith
  • Publication number: 20040080328
    Abstract: A probe card for testing an electrical element such as a semiconductor wafer or a printed wiring board includes a substrate with circuitry thereon, an encapsulant layer overlying the substrate and a multiplicity of leads extending upwardly from the substrate through the encapsulant layer to terminals, the terminals projecting above the encapsulant layer. The probe card can be engaged with the electronic element so that the tips of the leads bear on the contact pads of the electronic element, and so that the leads and encapsulant layer deform to accommodate irregularities in the electronic element or probe card. The card can be made by providing the substrate, a sacrificial layer and leads extending between the sacrificial layer and substrate, moving the substrate and sacrificial layer away from one another to deform the leads and injecting a curable material around the leads to form the encapsulant layer.
    Type: Application
    Filed: December 4, 2003
    Publication date: April 29, 2004
    Inventor: Joseph Fjelstad
  • Patent number: 6709899
    Abstract: A method of manufacturing a microelectronic assembly includes providing a first microelectronic element having a first surface and a plurality of terminals exposed at the first surface, providing a second microelectronic element having a top surface and a plurality of contacts exposed at the top surface, forming a plurality of conductive elastomeric posts which connect each of the contacts to one of the terminals, and injecting a compliant material between the first surface of the first microelectronic element and the top surface of the second microelectronic element to form a compliant layer.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: March 23, 2004
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Patent number: 6706973
    Abstract: An interposer for interconnection between microelectronic circuit panels has contacts at its surfaces. Each contact extends from a central conductor, and has a peripheral portion adapted to contract radially inwardly toward the central conductor response to a force applied by a contact pad defining a central hole on the engaged circuit panel. Thus, when the circuit panels are compressed with the interposers, the contacts contract radially inwardly and wipe across the pads. The wiping action facilitates bonding of the contacts to the pads, as by friction welding, or by a conductive bonding material carried on the contacts themselves.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: March 16, 2004
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Joseph Fjelstad