Patents by Inventor Joseph Fjelstad

Joseph Fjelstad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060084250
    Abstract: A method of making a microelectronic assembly includes providing a first microelectronic element having a first surface and a plurality of contacts exposed at the first surface; providing a second microelectronic element having a top surface and a plurality of contacts exposed at the top surface, forming a plurality of conductive elastomeric posts that connect at least some of the contacts of the first microelectronic element to at least some of the contacts of the second microelectronic element, and injecting a compliant material between the first surface of the first microelectronic element and the top surface of the second microelectronic element to form a compliant layer.
    Type: Application
    Filed: November 29, 2005
    Publication date: April 20, 2006
    Applicant: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Publication number: 20060040488
    Abstract: A method of electrically connecting a microelectronic component having a first surface bearing a plurality of contacts. The method including the steps of forming a subassembly by juxtaposing a connection component having a support structure and a plurality of elongated posts extending substantially parallel to one another from a first surface of the support structure with the microelectronic component so that the support structure overlies the surface of the component with the posts extending away from the component and electrically connecting the posts to the contacts of the microelectronic component.
    Type: Application
    Filed: October 24, 2005
    Publication date: February 23, 2006
    Applicant: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Publication number: 20060040522
    Abstract: A microelectronic interposer is made by providing a sacrificial layer over the surface of a planar body. Apertures are formed passing through the body and the sacrificial layer. A layer of an electrically conductive structural material is deposited in each of the apertures and over the sacrificial layer, proximate to each aperture to thereby form contacts. The sacrificial layer is removed leaving the contacts with outwardly flaring peripheral portions spaced vertically above the surface of the planar body.
    Type: Application
    Filed: August 25, 2005
    Publication date: February 23, 2006
    Applicant: Tessera, Inc.
    Inventors: Thomas Distefano, Joseph Fjelstad
  • Publication number: 20060035482
    Abstract: An electrical connector. An electrical connector comprising a connector body having a first channel and a first conductive element extending through the first channel in a first tip section. The first tip section having a first moment arm that, when forced in contact with a first conductive surface, twists the first conductive element to produce a torsion force. The torsion force holds the first tip section in contact with the first conductive surface.
    Type: Application
    Filed: May 6, 2005
    Publication date: February 16, 2006
    Inventors: Gary Yasumura, William Wiedemann, Joseph Fjelstad, Para Segaram, Kevin Grundy
  • Publication number: 20060034061
    Abstract: A signal-segregating connector for use in a system having a printed circuit board, a first electrical structure and a second electrical structure. The connector includes a first set of conductive elements to convey signals between the first electrical structure and the printed circuit board, and a second set of conductive elements to convey signals between the first electrical structure and the second electrical structure.
    Type: Application
    Filed: April 1, 2005
    Publication date: February 16, 2006
    Inventors: Kevin Grundy, Gary Yasumura, Joseph Fjelstad, William Wiedemann, Para Segaram
  • Patent number: 6978538
    Abstract: A microelectronic interposer is made by providing a sacrificial layer over the surface of a planar body. Apertures are formed passing through the body and the sacrificial layer. A layer of an electrically conductive structural material is deposited in each of the apertures and over the sacrificial layer, proximate to each aperture to thereby form contacts. The sacrificial layer is removed leaving the contacts with outwardly flaring peripheral portions spaced vertically above the surface of the planar body.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: December 27, 2005
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Joseph Fjelstad
  • Patent number: 6972495
    Abstract: An assembly including a first microelectronic element having a first surface and a plurality of contacts exposed at the first surface; a second microelectronic element having a top surface and a plurality of contacts exposed at the top surface; and conductive elastomeric posts formed by curing a conductive elastomeric material, wherein each of the contacts of the first microelectronic element is respectively aligned with one of the contacts of the second microelectronic element, and further wherein at least some of the contacts of the first element are connected to the respectively aligned contacts of the second element by the conductive elastomeric material.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: December 6, 2005
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Publication number: 20050239300
    Abstract: An electrical connector comprised of a plurality of electrical contacts arranged in a stair-step configuration designed to mate with electrical components having electrical contacts arranged in a stair-step configuration. A direct connect signaling system comprised of stair-step electrical connectors mated to stair-step printed circuit boards, other stair-step electrical components, or combinations thereof.
    Type: Application
    Filed: February 9, 2005
    Publication date: October 27, 2005
    Inventors: Gary Yasumura, Joseph Fjelstad, William Wiedemann, Para Segaram, Kevin Grundy
  • Publication number: 20050221680
    Abstract: An electrical interconnection device for establishing redundant contacts between the ends of two conductive elements to be mated, creating a electrical interconnection without capacitive stubs.
    Type: Application
    Filed: March 28, 2005
    Publication date: October 6, 2005
    Inventors: Gary Yasumura, Joseph Fjelstad, Kevin Grundy, William Wiedemann, Matthew Stepovich
  • Patent number: 6938338
    Abstract: Microelectronic contacts, such as flexible, tab-like, cantilever contacts, are provided with asperities disposed in a regular pattern. Each asperity has a sharp feature at its tip remote from the surface of the contact. As mating microelectronic elements are engaged with the contacts, a wiping action causes the sharp features of the asperities to scrape the mating element, so as to provide effective electrical interconnection and, optionally, effective metallurgical bonding between the contact and the mating element upon activation of a bonding material.
    Type: Grant
    Filed: April 17, 2003
    Date of Patent: September 6, 2005
    Assignee: Tessera, Inc.
    Inventors: Joseph Fjelstad, John W. Smith, Thomas H. DiStefano, James Zaccardi, A. Christian Walton
  • Publication number: 20050189640
    Abstract: Structures employed by a plurality of packages, printed circuit boards, connectors and interposers to create signal paths which reduce the deleterious signal quality issues associated with the use of through-holes. Disclosed structures can coexist with through-hole implementations.
    Type: Application
    Filed: February 9, 2005
    Publication date: September 1, 2005
    Inventors: Kevin Grundy, Joseph Fjelstad, Gary Yasumura, William Wiedemann, Para Segaram
  • Patent number: 6933610
    Abstract: In a semiconductor device having a semiconductor die without an ESD circuit and a separate ESD circuit and an external lead, the external lead is first bonded to the separate ESD circuit. Thereafter, the separate ESD circuit is bonded to the semiconductor die. As a result, in the process of bonding the semiconductor die, any ESD disturbance is absorbed by the ESD circuit. In addition, a semiconductor device such as a DDR DRAM memory device, has a chip carrier with a first surface having a plurality of leads and a second surface opposite to it with an aperture between them. A semiconductor die with a mounting surface and a bonding pad faces the second surface with the bonding pad in the aperture. An ESD circuit is mounted on the mounting surface in the aperture. A first electrical connector connects one of a plurality of leads to the ESD circuit and a second electrical connector connects the ESD circuit to the bonding pad.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: August 23, 2005
    Assignee: Silicon Pipe, Inc.
    Inventors: Para Kanagasabai Segaram, Joseph Fjelstad, Belgacem Haba
  • Publication number: 20050155223
    Abstract: A method of making a microelectronic assembly includes juxtaposing a first element having conductive leads thereon with a second element having contacts thereon, and wire bonding the conductive leads on the first element to the contacts on the second element so that elongated bonding wires extend between the conductive leads and the contacts. After the wire bonding step, the first and second elements are moved through a preselected displacement relative to one another so as to deform the bonding wires.
    Type: Application
    Filed: January 26, 2005
    Publication date: July 21, 2005
    Applicant: Tessera, Inc.
    Inventors: Joseph Fjelstad, Masud Beroz, John Smith, Belgacem Haba
  • Publication number: 20050146821
    Abstract: An IC package substrate having integral ESD protection features and elements and a method for construction of the same are disclosed
    Type: Application
    Filed: January 7, 2005
    Publication date: July 7, 2005
    Inventors: Joseph Fjelstad, Kevin Grundy
  • Publication number: 20050133922
    Abstract: Disclosed are tapered dielectric and conductor structures which provide controlled impedance interconnection while signal conductor lines transition from finer pitches to coarser pitches thereby obviating electrical discontinuities generally associated with changes of circuit contact pitch. Also disclosed are methods for the construction of the devices and applications therefore.
    Type: Application
    Filed: November 12, 2004
    Publication date: June 23, 2005
    Inventors: Joseph Fjelstad, Kevin Grundy, Para Segaram, Gary Yasumura
  • Patent number: 6906422
    Abstract: An element such as a semiconductor wafer or other body is provided with flexible leads, the tip ends of which project over the front surface of the element. The tips of the flexible leads are spaced apart from the front surface and are independently moveable with respect to the element. The flexible leads may be curved in a plane parallel to the front surface of the element, or may be curved so that the tip end of each flexible lead is disposed further from the front surface of the element than the main body of the flexible lead.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: June 14, 2005
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad
  • Publication number: 20050103522
    Abstract: Disclosed are stair stepped PCB structures which provide high performance, direct path, via-less interconnections between various elements of an electronic interconnection structure including, among others, IC packages and connectors.
    Type: Application
    Filed: November 15, 2004
    Publication date: May 19, 2005
    Inventors: Kevin Grundy, William Wiedemann, Joseph Fjelstad
  • Publication number: 20050093152
    Abstract: A cost effective, high performance, IC package assembly of the present invention comprises stair-stepped layers of redistribution circuits from at least one chip to terminals on any of multiple surfaces and levels of the IC package assembly. Critical path circuits of the assembly have no plated vias and are directly routed from interconnection terminals which are used to interconnect the package to the IC chip terminals by flip chip or wire bond methods.
    Type: Application
    Filed: October 12, 2004
    Publication date: May 5, 2005
    Inventors: Joseph Fjelstad, Para Segaram, Thomas Obenhuber, Inessa Obenhuber, Kevin Grundy, William Wiedemann
  • Publication number: 20050093127
    Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.
    Type: Application
    Filed: September 23, 2004
    Publication date: May 5, 2005
    Inventors: Joseph Fjelstad, Para Segaram, Thomas Obenhuber, Inessa Obenhuber, Kevin Grundy
  • Patent number: 6888168
    Abstract: A microelectronic package including an optoelectronic element having a front face including contacts and a rear surface; flexible conductive leads having first ends connected to the contacts and second ends connected to conductive pads adjacent the optoelectronic element; and an at least partially transparent encapsulant covering the optoelectronic element, the flexible leads and the conductive pads, the conductive pads being exposed on a bottom surface of the encapsulant, the bottom surface of the encapsulant defining a bottom of the package, wherein the encapsulant at the bottom of the package extends between the conductive pads.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: May 3, 2005
    Assignee: Tessera, Inc.
    Inventor: Joseph Fjelstad