Patents by Inventor Juergen Pille
Juergen Pille has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10529388Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.Type: GrantFiled: August 29, 2018Date of Patent: January 7, 2020Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Patent number: 10388357Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.Type: GrantFiled: December 5, 2017Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz
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Publication number: 20190251221Abstract: Generating design data for manufacturing a logic array of a semiconductor circuit from specification data describing the logic array. The specification is transformed into structured specification data including objects corresponding to circuit cells of a first type and logic specification data specifying the logic circuitry to be included in the logic array, and into structure data including placing and routing information concerning the circuit cells of the first type. A determination is made of circuit cells of a second type from the logic specification data. The circuit cells of the first type are pre-placed and routed based on the structure data. The circuit cells of second type are automatically placed and routed.Type: ApplicationFiled: April 24, 2019Publication date: August 15, 2019Inventors: Albert Frisch, Thomas Kalla, Juergen Pille, Philipp Salz
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Publication number: 20190228811Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.Type: ApplicationFiled: April 1, 2019Publication date: July 25, 2019Inventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz
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Patent number: 10318688Abstract: Generating design data for manufacturing a logic array of a semiconductor circuit from specification data describing the logic array. The specification is transformed into structured specification data including objects corresponding to circuit cells of a first type and logic specification data specifying the logic circuitry to be included in the logic array, and into structure data including placing and routing information concerning the circuit cells of the first type. A determination is made of circuit cells of a second type from the logic specification data. The circuit cells of the first type are pre-placed and routed based on the structure data. The circuit cells of second type are automatically placed and routed.Type: GrantFiled: March 27, 2017Date of Patent: June 11, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Albert Frisch, Thomas Kalla, Juergen Pille, Philipp Salz
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Patent number: 10210923Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.Type: GrantFiled: July 12, 2017Date of Patent: February 19, 2019Assignee: International Business Machines CorporationInventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz
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Patent number: 10204674Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.Type: GrantFiled: December 22, 2017Date of Patent: February 12, 2019Assignee: International Business Machines CorporationInventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz
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Publication number: 20190019549Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.Type: ApplicationFiled: December 22, 2017Publication date: January 17, 2019Inventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz
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Publication number: 20190019548Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.Type: ApplicationFiled: December 5, 2017Publication date: January 17, 2019Inventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz
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Publication number: 20190019547Abstract: In an approach to activating at least one memory core circuit of a plurality of memory core circuits in an integrated circuit, one or more computer processors activate a clock signal of a currently selected memory core circuit. The one or more computer processors activate the clock signal of a previously selected memory core circuit to allow the previously selected memory core circuit to be set to a deselected operating mode. The one or more computer processors forward an output bit generated by a memory core circuit selected from a plurality of memory core circuits to a multiplexed bit line.Type: ApplicationFiled: July 12, 2017Publication date: January 17, 2019Inventors: Thomas Kalla, Jens Noack, Juergen Pille, Philipp Salz
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Publication number: 20180374517Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.Type: ApplicationFiled: August 29, 2018Publication date: December 27, 2018Applicant: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Patent number: 10096346Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.Type: GrantFiled: July 19, 2017Date of Patent: October 9, 2018Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Publication number: 20180068043Abstract: Generating design data for manufacturing a logic array of a semiconductor circuit from specification data describing the logic array. The specification is transformed into structured specification data including objects corresponding to circuit cells of a first type and logic specification data specifying the logic circuitry to be included in the logic array, and into structure data including placing and routing information concerning the circuit cells of the first type. A determination is made of circuit cells of a second type from the logic specification data. The circuit cells of the first type are pre-placed and routed based on the structure data. The circuit cells of second type are automatically placed and routed.Type: ApplicationFiled: March 27, 2017Publication date: March 8, 2018Inventors: Albert Frisch, Thomas Kalla, Juergen Pille, Philipp Salz
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Patent number: 9837142Abstract: A memory cell readable through a bit line and addressable through a word line can be stressed by applying a stress voltage to the bit line for a stress voltage time, and addressing the memory cell through the word line for an addressing time included within the stress voltage time. The memory cell can be tested by writing a data value into the memory cell, stressing the memory cell, reading the stored value from the memory cell, and determining whether the stored value corresponds to the data value. A testable memory array can include a memory cell addressable through a word line and readable through a bit line, a precharge circuit, a stress circuit, and an array built-in self test (ABIST) circuit. The ABIST circuit can be configured to stress the memory cell by applying a stress signal to the stress circuit.Type: GrantFiled: July 12, 2016Date of Patent: December 5, 2017Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Michael B. Kugel, Stefan Payer, Wolfgang Penth, Juergen Pille, Tobias Werner
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Publication number: 20170316812Abstract: A current sense amplifier is provided. The amplifier comprises a first cross coupled inverter, a second cross coupled inverter, and a transmission gate. The first cross coupled inverter has a first source coupled to sense current input. The second cross coupled inverter has a second source coupled to a reference current input. The transmission gate comprises a first transmission end, a second transmission end, and a gate input. The first transmission end is operatively coupled to a first input of the first cross coupled inverter. The second transmission end is operatively coupled to a second input of the second cross coupled inverter. The gate input is operatively coupled to the control line input. Each cross coupled inverter is configured for switching a coupling of the sense current input and the reference current input.Type: ApplicationFiled: July 19, 2017Publication date: November 2, 2017Applicant: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Patent number: 9805823Abstract: A memory cell readable through a bit line and addressable through a word line can be stressed by applying a stress voltage to the bit line for a stress voltage time, and addressing the memory cell through the word line for an addressing time included within the stress voltage time. The memory cell can be tested by writing a data value into the memory cell, stressing the memory cell, reading the stored value from the memory cell, and determining whether the stored value corresponds to the data value. A testable memory array can include a memory cell addressable through a word line and readable through a bit line, a precharge circuit, a stress circuit, and an array built-in self test (ABIST) circuit. The ABIST circuit can be configured to stress the memory cell by applying a stress signal to the stress circuit.Type: GrantFiled: January 25, 2017Date of Patent: October 31, 2017Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Michael B. Kugel, Stefan Payer, Wolfgang Penth, Juergen Pille, Tobias Werner
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Patent number: 9761286Abstract: A current sense amplifier is provided comprising a reference current input terminal, a control line input terminal, a sense current input terminal and a first output terminal. The amplifier further comprises a first NAND gate comprising first and second gate input terminals, and a second output terminal being coupled to the first output terminal of the amplifier. The amplifier also comprises two cross coupled inverters each comprising an n-FET, an n-FET input terminal, and each n-FET having a respective source. The amplifier further comprises a transmission gate comprising two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal.Type: GrantFiled: August 24, 2016Date of Patent: September 12, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Patent number: 9704567Abstract: A memory cell that is readable through a bit line and addressable through a word line can be stressed using a method that includes addressing the memory cell, through the word line, for an addressing time. The memory cell can be stressed by applying a stress voltage to the bit line for a stress voltage time that overlaps with the addressing time for a stress time ?t. A method for testing a memory cell can include writing a data value into the memory cell, stressing the memory cell, reading a stored value from the memory cell and determining whether the stored value corresponds to the data value. A testable memory array can include at least one memory cell that is addressable through a word line and readable through a bit line and a stress circuit for applying a stress voltage to the bit line.Type: GrantFiled: July 12, 2016Date of Patent: July 11, 2017Assignee: International Business Machines CorporationInventors: Michael B. Kugel, Stefan Payer, Wolfgang Penth, Juergen Pille
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Publication number: 20170084314Abstract: Single ended bitline current sense amplifier for SRAM applications. The present disclosure relates to current sense read amplifier for use as a read amplifier in a memory arrangement of memory cell groups, wherein in each of the memory cell groups cells includes at least one read port connected to a read amplifier by a bitline, and wherein said read amplifiers are connected to a data output. The current sense read amplifier includes a voltage regulator to keep a bitline voltage at a constant voltage level below a power supply voltage and above a ground, a measurement circuit to detect a high current value and a low current value in a input signal, and a generator to generate a high voltage level output signal when the high current value input is detected and to generate a low voltage level output signal when the low current level value is detected.Type: ApplicationFiled: September 17, 2015Publication date: March 23, 2017Inventors: Alexander Fritsch, Shankar Kalyanasundaram, Michael Kugel, Juergen Pille
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Patent number: 9595304Abstract: The invention relates to a current sense amplifier (103) comprising a reference current input terminal (109), a sense control line input terminal (125), a sense current input terminal (108), a first output terminal (106), and a second output terminal (107).Type: GrantFiled: December 4, 2015Date of Patent: March 14, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Fritsch, Ulrich Krauch, Michael B. Kugel, Juergen Pille