Abstract: A structure and method to reduce leakage of a Static Random Access Memory (SRAM) array, wherein the array is subdivided into a set of sub-arrays, whose supply voltages can be controlled independently using a single voltage regulation circuit dedicated to the entire SRAM array. A switch fabric enables independent switching of individual sub-arrays between a virtual ground level and a system ground level based on whether the sub-array is operating in power saving mode or a high performance mode to reduce leakage current when a sub-array is configured in a power saving mode.

Abstract: A method and system for maintaining Static Random Access Memory (SRAM) functionality while simultaneously screening for leakage paths from bitline to ground during Float Mode operation. The SRAM configuration enables SRAM cell selection for a read or write operation. In response to the SRAM cell selection, a group of pre-charge (PCHG) signals are provided with a high value. When selection is made from a top sub-group of SRAM cells, a corresponding bitline, “BLT_TOP”, takes a value which reflects a state stored in the selected cell. In addition, the bitline corresponding to the bottom sub-group of cells, “BLT_BOT”, takes a high value. If there is a leakage defect, BLT_BOT drops to a low value. With no leakage defect, the data stored in the selected cell is determined based on the result of a logical NAND operation including the respective states indicated by the BLT_TOP and by the BLT_BOT.

Abstract: A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/our preceding sub tree.

Abstract: A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output.

Abstract: A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.

Abstract: A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage in accordance an input signal, where the input signal depends on at least one of an operation to be performed and component performing the operation.

Abstract: A design structure embodied in a machine readable medium to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The design structure includes a write circuit for an SRAM cell or an SRAM array. The write circuit includes a gate to switch the write circuit on and off. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage.

Abstract: A method and system for maintaining Static Random Access Memory (SRAM) functionality while simultaneously screening for leakage paths from bitline to ground during Float Mode operation. The SRAM configuration enables SRAM cell selection for a read or write operation. In response to the SRAM cell selection, a group of pre-charge (PCHG) signals are provided with a high value. When selection is made from a top sub-group of SRAM cells, a corresponding bitline, “BLT_TOP”, takes a value which reflects a state stored in the selected cell. In addition, the bitline corresponding to the bottom sub-group of cells, “BLT_BOT”, takes a high value. If there is a leakage defect, BLT_BOT drops to a low value. With no leakage defect, the data stored in the selected cell is determined based on the result of a logical NAND operation including the respective states indicated by the BLT_TOP and by the BLT_BOT.

Abstract: The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element (20) for shifting a voltage level of a charge storage element (50) for storing a charge necessary to generate a boosted voltage (Vb), a feedback element (30) for controlling the switching state of a charging element (40), wherein the charging element (40) is actively switchable between a turned-off state during a first time interval and a turned-on state during a second time interval, and an output port (14) for supplying the boost voltage to at least one wordline-driver circuit (100) of a memory device (200). The invention relates also to an operation method for such a wordline booster circuit as well as a memory array implementation on an integrated circuit, especially an SRAM memory array, with a wordline booster circuit.

Abstract: A method to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage. An SRAM cell, an SRAM array plus a write circuit used to perform the method are also described.

Abstract: A structure and method to reduce leakage of a Static Random Access Memory (SRAM) array, wherein the array is subdivided into a set of sub-arrays, whose supply voltages can be controlled independently using a single voltage regulation circuit dedicated to the entire SRAM array. A switch fabric enables independent switching of individual sub-arrays between a virtual ground level and a system ground level based on whether the sub-array is operating in power saving mode or a high performance mode to reduce leakage current when a sub-array is configured in a power saving mode.

Abstract: A programmable Local Clock Buffer has a single inverter between the clock input and the delayed clock output. A transistor switch modulates the single inverter stage between a clock signal transmit state and a non-transmitting state. A combination of delay select bits control the timing of the beginning and ending of the transmit state of the inverter relative to the clock input via the transistor switch.

Abstract: A design structure embodied in a machine readable medium to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The design structure includes a write circuit for an SRAM cell or an SRAM array. The write circuit includes a gate to switch the write circuit on and off. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage.

Abstract: A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage in accordance an input signal, where the input signal depends on at least one of an operation to be performed and component performing the operation.

Abstract: A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read.

Abstract: According to the present invention an automated layout generator is provided for routing and designing an LSI (Large Scale Integrated Circuit). First, at least one generic of an instance of a book to be connected is located on the chip, wherein a generic of an instance is an area defined according to the measurements of said instance. Then, an initial route to said instance is generated by optimizing the route to the corresponding generic according to given design rules. Thereby, an optimized pin location is determined for said instance. Then, on the basis of said optimized pin location a layout for said instance is generated in place of the corresponding generic. Finally, the actually generated pin is connected with the corresponding end of the initial route.

Abstract: A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), Which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal, of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/our preceding sub tree.

Abstract: According to the present invention an automated method is provided for routing and designing an LSI (Large Scale Integrated Circuit). First, at least one generic of an instance of a book to be connected is located on the chip, wherein a generic of an instance is an area defined according to the measurements of said instance. Then, an initial route to said instance is generated by optimizing the route to the corresponding generic according to given design rules. Thereby, an optimized pin location is determined for said instance. Then, on the basis of said optimized pin location a layout for said instance is generated in place of the corresponding generic. Finally, the actually generated pin is connected with the corresponding end of the initial route.

Abstract: The invention proposes a Random Access Memory (1) with a plurality of symmetrical memory cells (2) which are connected in groups to complementary bit lines (blc, blt), and the complementary bit lines (blc, blt) are coupled through a cross coupled device (31, 32), and the groups of memory cells are connected to complementary global data lines (data_c, data_t) used to provide data to a selected cell of the group of memory cells. The Random Access Memory is characterized in that switches (33, 34) are provided that deactivate the cross coupled device, wherein the switches (33, 34) are driven by the complementary global data lines (data_c, data_t). The invention relates further on to a computer comprising such a Random Access Memory.

Abstract: A method to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage. An SRAM cell, an SRAM array plus a write circuit used to perform the method are also described.