Patents by Inventor Juergen Pille
Juergen Pille has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9589604Abstract: Single ended bitline current sense amplifier for SRAM applications. The present disclosure relates to current sense read amplifier for use as a read amplifier in a memory arrangement of memory cell groups, wherein in each of the memory cell groups cells includes at least one read port connected to a read amplifier by a bitline, and wherein said read amplifiers are connected to a data output. The current sense read amplifier includes a voltage regulator to keep a bitline voltage at a constant voltage level below a power supply voltage and above a ground, a measurement circuit to detect a high current value and a low current value in a input signal, and a generator to generate a high voltage level output signal when the high current value input is detected and to generate a low voltage level output signal when the low current level value is detected.Type: GrantFiled: September 17, 2015Date of Patent: March 7, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Shankar Kalyanasundaram, Michael Kugel, Juergen Pille
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Patent number: 9552851Abstract: A current sense amplifier comprises a reference current input terminal, a control line input terminal, a sense current input terminal, an output terminal, a first NAND gate, a transmission gate, and two cross coupled inverters each comprising a n-FET. The first NAND gate comprises an output terminal being coupled to the output terminal of the amplifier. The transmission gate comprises two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal. Sources of the n-FETs are coupled to the sense current input terminal and the reference current input terminal, respectively. One of the transmission terminals is coupled to an input terminal of one of the inverters and the other transmission terminal is coupled to an input terminal of the other inverter. The input terminals of the first NAND gate are coupled to the control line terminal and one of the input terminals of the inverters, respectively.Type: GrantFiled: August 31, 2015Date of Patent: January 24, 2017Assignee: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Patent number: 9537474Abstract: Electronic circuits and memory circuits are provided for implementing a method for transforming a chip clock signal to a local clock signal. The method includes: generating a first clock signal in response to the chip clock signal, a first control signal and a second control signal; generating a second clock signal by delaying the first clock signal with a second clock delay; generating the first control signal and the second control signal by delaying the second clock signal with a pulse width delay, where the first control signal goes from high-to-low with a control signal delay after the second control signal goes from high-to-low, and vice versa; and generating the local clock signal based on the second clock signal.Type: GrantFiled: October 26, 2015Date of Patent: January 3, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yuen Hung Chan, Juergen Pille, Rolf Sautter, Tobias Werner
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Publication number: 20160365130Abstract: A current sense amplifier is provided comprising a reference current input terminal, a control line input terminal, a sense current input terminal and a first output terminal. The amplifier further comprises a first NAND gate comprising first and second gate input terminals, and a second output terminal being coupled to the first output terminal of the amplifier. The amplifier also comprises two cross coupled inverters each comprising an n-FET, an n-FET input terminal, and each n-FET having a respective source. The amplifier further comprises a transmission gate comprising two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal.Type: ApplicationFiled: August 24, 2016Publication date: December 15, 2016Applicant: International Business Machines CorporationInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Publication number: 20160344377Abstract: Electronic circuits and memory circuits are provided for implementing a method for transforming a chip clock signal to a local clock signal. The method includes: generating a first clock signal in response to the chip clock signal, a first control signal and a second control signal; generating a second clock signal by delaying the first clock signal with a second clock delay; generating the first control signal and the second control signal by delaying the second clock signal with a pulse width delay, where the first control signal goes from high-to-low with a control signal delay after the second control signal goes from high-to-low, and vice versa; and generating the local clock signal based on the second clock signal.Type: ApplicationFiled: October 26, 2015Publication date: November 24, 2016Inventors: Yuen Hung CHAN, Juergen PILLE, Rolf SAUTTER, Tobias WERNER
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Patent number: 9401698Abstract: Electronic circuits and memory circuits are provided for implementing a method for transforming a chip clock signal to a local clock signal. The method includes: generating a first clock signal in response to the chip clock signal, a first control signal and a second control signal; generating a second clock signal by delaying the first clock signal with a second clock delay; generating the first control signal and the second control signal by delaying the second clock signal with a pulse width delay, where the first control signal goes from high-to-low with a control signal delay after the second control signal goes from high-to-low, and vice versa; and generating the local clock signal based on the second clock signal.Type: GrantFiled: May 20, 2015Date of Patent: July 26, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yuen Hung Chan, Juergen Pille, Rolf Sautter, Tobias Werner
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Publication number: 20160072461Abstract: A current sense amplifier comprises a reference current input terminal, a control line input terminal, a sense current input terminal, an output terminal, a first NAND gate, a transmission gate, and two cross coupled inverters each comprising a n-FET. The first NAND gate comprises an output terminal being coupled to the output terminal of the amplifier. The transmission gate comprises two transmission terminals and a gate terminal. The gate terminal is coupled to the control line terminal. Sources of the n-FETs are coupled to the sense current input terminal and the reference current input terminal, respectively. One of the transmission terminals is coupled to an input terminal of one of the inverters and the other transmission terminal is coupled to an input terminal of the other inverter. The input terminals of the first NAND gate are coupled to the control line terminal and one of the input terminals of the inverters, respectively.Type: ApplicationFiled: August 31, 2015Publication date: March 10, 2016Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Fritsch, Michael Kugel, Juergen Pille, Dieter Wendel
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Patent number: 9098659Abstract: A clock stretcher mechanism is provided for shifting a rising edge of a negative active global clock signal beyond a rising edge of a feedback path signal. A negative active global clock signal and a clock chopper signal are received in a base block. First base block circuitry modifies the clock chopper signal in order to form the feedback path signal. Second base block circuitry shifts the rising edge of the negative active global clock signal beyond the rising edge of the feedback path signal using a delay negative active global clock signal.Type: GrantFiled: January 21, 2014Date of Patent: August 4, 2015Assignee: International Business Machines CorporationInventors: Osama Dengler, Thomas Froehnel, Juergen Pille, Rolf Sautter
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Patent number: 8942052Abstract: A voltage selection mechanism is provided for switching between multiple voltages without causing a direct current (DC) that may further stress storage elements due to excessive power consumption and electro-migration effects. The voltage selection mechanism comprises cross-coupled circuitry, which comprises a first positive-channel field effect transistor (PFET) and a second PFET. The voltage selection mechanism further comprises diode circuitry, which comprises a third PFET and a fourth PFET.Type: GrantFiled: November 21, 2012Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: William V. Huott, Michael Kugel, Juergen Pille, Rolf Sautter, Dieter Wendel
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Publication number: 20140140157Abstract: A voltage selection mechanism is provided for switching between multiple voltages without causing a direct current (DC) that may further stress storage elements due to excessive power consumption and electro-migration effects. The voltage selection mechanism comprises cross-coupled circuitry, which comprises a first positive-channel field effect transistor (PFET) and a second PFET. The voltage selection mechanism further comprises diode circuitry, which comprises a third PFET and a fourth PFET.Type: ApplicationFiled: November 21, 2012Publication date: May 22, 2014Applicant: International Business Machines CorporationInventors: William V. Huott, Michael Kugel, Juergen Pille, Rolf Sautter, Dieter Wendel
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Publication number: 20140137070Abstract: A clock stretcher mechanism is provided for shifting a rising edge of a negative active global clock signal beyond a rising edge of a feedback path signal. A negative active global clock signal and a clock chopper signal are received in a base block. First base block circuitry modifies the clock chopper signal in order to form the feedback path signal. Second base block circuitry shifts the rising edge of the negative active global clock signal beyond the rising edge of the feedback path signal using a delay negative active global clock signal.Type: ApplicationFiled: January 21, 2014Publication date: May 15, 2014Applicant: International Business Machines CorporationInventors: Osama Dengler, Thomas Froehnel, Juergen Pille, Rolf Sautter
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Patent number: 8493812Abstract: A technique for generating an adjustable boost voltage for a device includes charging, using first and second switches, a capacitor to a first voltage during a charging phase. The technique also includes stacking, using a third switch, a second voltage onto the first voltage across the capacitor in a boost phase to generate a boost voltage. In this case, the boost voltage is applied to a driver circuit of the device only during the boost phase and at least one of the first and second voltages is adjustable, thereby making the boost voltage adjustable.Type: GrantFiled: October 28, 2010Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Osama Dengler, Alexander Fritsch, Wolfgang Penth, Juergen Pille
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Publication number: 20130091375Abstract: A clock stretcher mechanism is provided for shifting a rising edge of a negative active global clock signal beyond a rising edge of a feedback path signal. A negative active global clock signal and a clock chopper signal are received in a base block. First base block circuitry modifies the clock chopper signal in order to form the feedback path signal. Second base block circuitry shifts the rising edge of the negative active global clock signal beyond the rising edge of the feedback path signal using a delay negative active global clock signal.Type: ApplicationFiled: October 10, 2011Publication date: April 11, 2013Applicant: International Business Machines CorporationInventors: Osama Dengler, Thomas Froehnel, Juergen Pille, Rolf Sautter
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Patent number: 8237481Abstract: A programmable Local Clock Buffer has a single inverter between the clock input and the delayed clock output. A transistor switch modulates the single inverter stage between a clock signal transmit state and a non-transmitting state. A combination of delay select bits control the timing of the beginning and ending of the transmit state of the inverter relative to the clock input via the transistor switch.Type: GrantFiled: April 25, 2008Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Yuen H. Chan, Rolf Sautter, Michael J. Lee, Juergen Pille
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Publication number: 20120106237Abstract: A technique for generating an adjustable boost voltage for a device includes charging, using first and second switches, a capacitor to a first voltage during a charging phase. The technique also includes stacking, using a third switch, a second voltage onto the first voltage across the capacitor in a boost phase to generate a boost voltage. In this case, the boost voltage is applied to a driver circuit of the device only during the boost phase and at least one of the first and second voltages is adjustable, thereby making the boost voltage adjustable.Type: ApplicationFiled: October 28, 2010Publication date: May 3, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: OSAMA DENGLER, ALEXANDER FRITSCH, WOLFGANG PENTH, JUERGEN PILLE
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Patent number: 7936198Abstract: A programmable clock control circuit includes a base block, a chop block, and a pulse width variation block coupled between the chop block and the base block that receives the chop block output and provides a pulse width variation output to the base block. The pulse width variation block is programmable to vary the chop block output to provide at least three different output pulse widths. The circuit also includes a clock delay block coupled an output of the base block to delay the output pulse and having a clock signal output.Type: GrantFiled: December 30, 2008Date of Patent: May 3, 2011Assignee: International Business Machines CorporationInventors: Rolf Sautter, Michael Ju Hyeok Lee, Yuen Hung Chan, Juergen Pille
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Patent number: 7921388Abstract: The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element (20) for shifting a voltage level of a charge storage element (50) for storing a charge necessary to generate a boosted voltage (Vb), a feedback element (30) for controlling the switching state of a charging element (40), wherein the charging element (40) is actively switchable between a turned-off state during a first time interval and a turned-on state during a second time interval, and an output port (14) for supplying the boost voltage to at least one wordline-driver circuit (100) of a memory device (200). The invention relates also to an operation method for such a wordline booster circuit as well as a memory array implementation on an integrated circuit, especially an SRAM memory array, with a wordline booster circuit.Type: GrantFiled: August 30, 2007Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: Sebastian Ehrenreich, Juergen Pille, Otto Torreiter
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Patent number: 7844871Abstract: A method for testing memory elements of an integrated circuit with an array built in self test (ABIST) comprises providing an ABIST interface to interface between an ABIST engine and a plurality of latches of a memory element under test, providing a multiplex (MUX) stage adjacent a scan input port of each latch, providing functional signal inputs to a data input port of the latches, setting the latches to an ABIST mode by activating an ABIST enable signal and delivering the ABIST enable signal to each of the latches, generating a plurality of ABIST test signals with the ABIST engine, applying the ABIST test signals in parallel to the scan input ports of the latches, determining whether one or more test patterns have been executed, and setting the latches to a normal run mode by deactivating the ABIST enable signal.Type: GrantFiled: November 11, 2008Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: Uwe Brandt, Stefan Buettner, Werner Juchmes, Juergen Pille
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Patent number: 7844799Abstract: A method and system for operating a high frequency out-of-order processor with increased pipeline length. A new scheme is disclosed to reduce the pipeline by the detection and exploitation of so called “no dependency” for an instruction. A “no dependency” signal tells that all required source data is available for the instruction at least one cycle before the source data valid bit(s) are inserted into the issue queue. Therefore, one or more stages of the pipeline are bypassed.Type: GrantFiled: December 20, 2001Date of Patent: November 30, 2010Assignee: International Business Machines CorporationInventors: Jens Leenstra, Antje Mueller, Juergen Pille, Dieter Wendel
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Patent number: 7813163Abstract: A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read.Type: GrantFiled: August 13, 2008Date of Patent: October 12, 2010Assignee: International Business Machines CorporationInventors: Juergen Pille, Otto Wagner, Sebastian Ehrenreich, Rolf Sautter