Abstract: The present disclosure provides methods and structures to prevent cracks in redistribution layers. A redistribution structure according to the present disclosure includes a first polymer layer disposed over a silicon substrate, a first contact via disposed in the first polymer layer, a second polymer layer disposed over the first contact via, a first redistribution layer including a first conductive pad disposed on the second polymer layer and a second contact via extending through the second polymer layer to physical contact the first contact via, a third polymer layer disposed over the first redistribution layer, a second redistribution layer including a second conductive pad disposed on the third polymer layer and a plurality of third contact vias extending through the third polymer layer to physically contact the first conductive pad. The first conductive pad has at least one opening and the second conductive pad has at least one opening.

Abstract: The embodiments provide a method for reading and writing and a memory device. The method includes: applying a read command to the memory device, the read command pointing to address information; reading data to be read out from a memory cell corresponding to the address information pointed to by the read command; and storing the address information pointed to by the read command into a memory bit of a preset memory space if an error occurs in the data to be read out, wherein the preset memory space is provided with a plurality of the memory bits, and each of the plurality of memory bits is associated with a spare memory cell.

Abstract: An electrochemical apparatus, includes an electrode assembly having a positive electrode plate; a negative electrode plate including a negative electrode current collector, a second active material having a second active substance, and a first active material layer having a first active substance located between the negative electrode current collector and the second active material layer; and a separator disposed between the positive electrode plate and the negative electrode plate. Compacted density of the first active material layer is greater than compacted density of the second active material layer. Sphericity of the first active substance is smaller than sphericity of the second active substance. The separator includes a porous substrate layer and a first coating layer disposed on at least one surface of the porous substrate layer facing the second active material layer. 20 N/m?Adhesion between the separator and the negative electrode plate?2 N/m.

Abstract: The present disclosure provides a sense amplifier, a memory, and a method for controlling a sense amplifier, relating to the technical field of semiconductor memories. The sense amplifier comprises: an amplification module; and an offset voltage storage unit electrically connected to the amplification module; wherein, in an offset cancellation stage of the sense amplifier, the sense amplifier is configured to comprise a current mirror structure to store an offset voltage of the amplification module in an offset voltage storage unit. The present disclosure can realize the offset cancellation of the sense amplifier.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes: a die having a frontside and a backside; a first redistribution layer (RDL) structure disposed on the backside of the die; a second RDL structure disposed on and electrically connected to the frontside of the die; a through integrated fan-out via (TIV) disposed lateral to the die and extending to electrically connect the first and the second RDL structures; a molding compound disposed between the first and second RDL structures; an enhancement layer disposed on the second RDL structure; a plurality of pre-solder bumps; and a plurality of solder balls disposed on and electrically connected to the second RDL structure. The enhancement layer includes a plurality of cascaded openings electrically connected to the first RDL structure. Each of the pre-solder bumps is disposed in one of the cascaded openings.

Abstract: A laser grooving operation is performed to form a plurality of grooves in a semiconductor die prior to attaching the semiconductor die to a semiconductor device package substrate. In addition to forming a first groove through which blade sawing is to be performed to separate the semiconductor die from other semiconductor dies, a second groove may be formed between the first groove and a seal ring of the semiconductor die. The second groove is configured to contain any potential delamination that might otherwise propagate to an active region of the semiconductor die. Accordingly, the second groove and the associated laser grooving operation described herein may reduce the likelihood of delamination that might otherwise be caused by swelling and/or expansion in a molding compound formed around the semiconductor die after the semiconductor die is attached to the semiconductor device package substrate.

Abstract: Provided are a band-pass filter circuit and a multiplexer. The band-pass filter circuit includes an electromagnetic LC filter circuit and acoustic resonance units. At least one of the acoustic resonance units each includes at least one first acoustic resonator and at least one second acoustic resonator. The first acoustic resonator is connected in series between the band-pass filter circuit and the electromagnetic LC filter circuit. Each of the at least one second acoustic resonator is connected to a terminal of the at least one first acoustic resonator, where the first terminal of the band-pass filter circuit serves as an input terminal or output terminal of the band-pass filter circuit. One or more of the acoustic resonance units are connected on an input side of the electromagnetic LC filter circuit; and the remaining of the acoustic resonance units are connected on an output side of the electromagnetic LC filter circuit.

Abstract: An adhesion layer may be formed over portions of a redistribution layer (RDL) in a redistribution structure of a semiconductor device package. The portions of the RDL over which the adhesion layer is formed may be located in the “shadow” of (e.g., the areas under and/or over and within the perimeter of) one or more TIVs that are connected with the redistribution layer structure. The adhesion layer, along with a seed layer on which the portions of the RDL are formed, encapsulate the portions of the RDL in the shadow of the one or more TIVs, which promotes and/or increases adhesion between the portions of the RDL and the polymer layers of the redistribution structure.

Abstract: A memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips include a first storage chip set and a second storage chip set, the storage chips in the first storage chip set are configured to perform information interaction with the control chip by adopting a first clock signal, the storage chips in the second storage chip set are configured to perform information interaction with the control chip by adopting a second clock signal, and phase of the first clock signal is different from phase of the second clock signal.

Abstract: A method of scheduling input/output operations for a storage system including determining a deadline for a storage operation, wherein the deadline is dependent on an expected latency of the storage operation; adding the storage operation to a queue of storage operations; and reordering the queue dependent upon the deadline of the storage operation and one or more deadlines of one or more storage operations in the queue of storage operations.

Abstract: A sense amplifier includes an amplification module and a control module electrically connected to the amplification module. Herein, in a case of reading a data in a memory cell on a first bit line, at an offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a first diode structure, a first current mirror structure, and a first inverter with an input terminal and an output terminal connected to each other. In a case of reading a data in a memory cell on a second bit line, at the offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a second diode structure, a second current mirror structure, and a second inverter with an input terminal and an output terminal connected to each other.

Abstract: A package structure is provided. The package structure includes a bottom die and a top die. The bottom die includes: a first active region surrounded by a first seal ring region; a first seal ring region including a bottom seal ring; and a first bonding layer disposed on a front side of the bottom die. The top die includes: a second active region surrounded by a second seal ring region; a second seal ring region including a top seal ring; and a second bonding layer disposed on a front side of the top die. The bottom die and the top die are bonded through hybrid bonding between the first bonding layer and the second bonding layer at an interface therebetween such that the bottom seal ring and the top seal ring are vertically aligned and are operable to form a continuous seal ring.

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, and an electronic device, which relate to the field of semiconductor device test technologies. The control chip includes a built-in self-test BIST circuit. The method is performed by the BIST circuit. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Abstract: A sense amplifier includes: an amplification circuit, configured to read data of a memory cell on a first bit line or a second bit line; and a first offset voltage storage cell and a second offset voltage storage cell, respectively and electrically connected to the amplification circuit, wherein in a case where the data in the memory cell on the first bit line is read, in an offset elimination stage of the sense amplifier, the sense amplifier is configured to store an offset voltage of the sense amplifier in the first offset voltage storage cell; and in a case where the data in the memory cell on the second bit line is read, in the offset elimination stage of the sense amplifier, the sense amplifier is configured to store the offset voltage of the sense amplifier in the second offset voltage storage cell.

Abstract: Embodiments of the present disclosure provide a test method and apparatus for a control chip, an electronic device, relating to the field of semiconductor device test technology. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, a memory chip can be used for storing test vectors for a control chip, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

Abstract: A sense amplifier, a memory and a method for controlling the sense amplifier are provided. The sense amplifier includes: an amplification module configured to read data in a storage unit on a first or second bit line; a control module electrically connected to the amplification module. When data in the storage unit on the first bit line is read, in a first amplification phase of the sense amplifier, the control module configures the amplification module to include a first current mirror structure and connects a mirror terminal of the first current mirror structure to the second bit line; when data in the storage unit on the second bit line is read, in the first amplification phase of the sense amplifier, the control module configures the amplification module to include a second current mirror structure and connects a mirror terminal of the second current mirror structure to the first bit line.

Abstract: The present disclosure describes a structure that joins semiconductor packages and a method for forming the structure. The structure includes an adhesion layer in contact with a first semiconductor package and a first joint pad in contact with the adhesion layer. The structure further includes a film layer disposed on the first semiconductor package and the first joint pad, where the film layer includes a slanted sidewall, the slanted sidewall covers an end portion of the adhesion layer and a first portion of the first joint pad, and the slanted sidewall exposes a second portion of the first joint pad. The structure further includes a solder ball attached to the second portion of the first joint pad and a second joint pad of a second semiconductor package.

Abstract: A semiconductor structure includes a first device and a second device bonded on the first device. The first device has a first sidewall distal to the second device and a second sidewall proximal to the second device. A surface roughness of the second sidewall is larger than a surface roughness of the first sidewall. The second device has a third sidewall proximal to the first device and a fourth sidewall distal to the first device. A surface roughness of the fourth sidewall is larger than a surface roughness of the third sidewall.

Abstract: Material properties of graphene can be leveraged to improve performance of interconnects in an integrated circuit. One way to circumvent challenges involved in depositing graphene onto a copper surface is to incorporate graphene into the bulk metal layer to create a hybrid metal/graphene interconnect structure. Such a hybrid structure can be created instead of, or in addition to, forming a graphene film on the metal surface as a metal capping layer. A first method for embedding graphene into a copper damascene layer is to alternate the metal fill process with graphene deposition to create a composite graphene matrix. A second method is to implant carbon atoms into a surface layer of metal. A third method is to disperse graphene flakes in a damascene copper plating solution to create a distributed graphene matrix. Any combination of these methods can be used to enhance conductivity of the interconnect.

Abstract: A graphene-clad metal interconnect extends material properties of graphene to both damascene and patterned interconnect structures at lower metal layers, leading to significant reductions in resistance. Graphene cladding can be used with or without a metal barrier/liner. Presence of a barrier/liner can serve to catalyze growth of an overlying graphene layer. Graphene may also be selectively grown on barrier surfaces. Fully integrated structures and process flows for integrated circuits with graphene-clad metallization are described.