Abstract: Each unit pixel includes a photoelectric converter, an n-type impurity region forming an accumulation diode together with the semiconductor region, the accumulation diode accumulating a signal charge generated by the photoelectric converter, an amplifier transistor including a gate electrode electrically connected to the impurity region, and an isolation region formed around the amplifier transistor and implanted with p-type impurities. The amplifier transistor includes an n-type source/drain region formed between the gate electrode and the isolation region, and a channel region formed under the gate electrode. A gap in the isolation region is, in a gate width direction, wider at a portion including the channel region than at a portion including the source/drain region.

Abstract: Each unit pixel includes a photoelectric converter formed above a semiconductor region, an amplifier transistor formed in the semiconductor region, and including a gate electrode connected to the photoelectric converter, a reset transistor configured to reset a potential of the gate electrode, and an isolation region formed in the semiconductor region between the amplifier transistor and the reset transistor to electrically isolate the amplifier transistor from the reset transistor. The amplifier transistor includes a source/drain region. The source/drain region has a single source/drain structure.

Abstract: An imaging device includes a semiconductor layer and a pixel cell. The pixel cell includes an impurity region of a first conductivity type, the impurity region located in the semiconductor layer, a photoelectric converter electrically connected to the impurity region and located above the semiconductor layer, a first transistor having a first gate, a first source and a first drain, one of the first source and the first drain electrically connected to the impurity region, a second transistor having a second gate of a second conductivity type different from the first conductivity type, a second source and a second drain, the second transistor including the impurity region as one of the second source and the second drain, the second gate electrically connected to the impurity region, and a third transistor having a third gate, a third source and a third drain, the third gate electrically connected to the photoelectric converter.

Abstract: An imaging device includes a unit pixel cell including: a semiconductor substrate including a first region exposed to a surface of the semiconductor substrate in a first area, and a second region directly adjacent to the first region and exposed to the surface in a second area; a photoelectric converter; a contact plug connected to the second region; a first transistor including the second region as one of a source and a drain, a first electrode covering a first portion of the first area, and a first insulation layer between the first electrode and the semiconductor substrate; a second electrode covering a second portion of the first area; and a second insulation layer between the second electrode and the semiconductor substrate. When seen in a direction perpendicular to the surface, a contact between the second region and the contact plug is located between the first electrode and the second electrode.

Abstract: An imaging device including a unit pixel cell comprising: a semiconductor substrate including a first conductivity type region of a first conductivity type, a first and second impurity regions of a second conductivity type provided in the first conductivity type region; a photoelectric converter located above the semiconductor substrate; and a first transistor including a gate electrode and at least a part of the second impurity region as a source or a drain. The first impurity region is at least partially located in a surface of the semiconductor substrate and electrically connected to the photoelectric converter. The second impurity region is electrically connected to the photoelectric converter via the first impurity region and has an impurity concentration lower than that of the first impurity region. The second impurity region at least partially overlaps the gate electrode in a plan view.

Abstract: An imaging device includes a semiconductor substrate; and a unit pixel cell provided to a surface of the semiconductor substrate. The unit pixel cell includes: a photoelectric converter that includes a pixel electrode and a photoelectric conversion layer located on the pixel electrode, the photoelectric converter converting incident light into electric charges; a charge detection transistor that includes a part of the semiconductor substrate and detects the electric charges; and a reset transistor that includes a first gate electrode and initializes a voltage of the photoelectric converter. The pixel electrode is located above the charge detection transistor. The reset transistor is located between the charge detection transistor and the pixel electrode. When viewed from a direction normal to the surface of the semiconductor substrate, the pixel electrode covers an entire portion of the first gate electrode.

Abstract: A solid-state imaging device has a plurality of imaging-purpose pixels and a plurality of focus detection-purpose pixels. Each of the imaging-purpose pixels are provided with a first lower electrode, a photoelectric conversion film formed on the first lower electrode, and an upper electrode formed on the photoelectric conversion film. Each of the focus detection-purpose pixels is provided with a second lower electrode, the photoelectric conversion film formed on the second lower electrode, and the upper electrode formed on the photoelectric conversion film. The area of the second lower electrode is smaller than the area of the first lower electrodes. The second lower electrode is provided on a position deviating from a pixel center of a corresponding focus detection-pixel, and two second lower electrodes corresponding to two focus detection purpose pixels included in the plurality of focus detection purpose pixels is arranged in mutually opposite directions.

Abstract: An imaging device includes: a unit pixel cell comprising: a photoelectric converter generating an electric signal and comprising a first and second electrodes and a photoelectric conversion film located therebetween, the first electrode being located on a light receiving side of the photoelectric conversion film, a signal detection circuit detecting the electric signal and comprising a first transistor and a second transistor that are connected to the second electrode, the first transistor amplifying the electric signal, and a capacitor circuit comprising a first capacitor and a second capacitor having a capacitance value larger than that of the first capacitor that are serially connected to each other, the capacitor circuit being provided between the second electrode and a reference voltage; and a feedback circuit comprising the first transistor and an inverting amplifier and negatively feeding back the electric signal to the second transistor via the first transistor and the inverting amplifier.

Abstract: An imaging device of the present disclosure includes: a unit pixel cell comprising a photoelectric converter converting incident light into signal charge, a semiconductor substrate, a charge storage region located in the semiconductor substrate and storing the signal charge, and a signal detection circuit detecting the signal charge; a feedback circuit negatively feeding back output of the signal detection circuit and comprising a signal line; and at least one wiring layer located between the semiconductor substrate and the photoelectric converter. The at least one wiring layer includes a portion of the signal line, the portion overlapping the unit pixel cell in a plan view. In the plan view, the portion is located on an opposite side from the charge storage region across a center line of the unit pixel cell, the center line being in parallel with a direction in which the signal line extends.

Abstract: An imaging device including a unit pixel cell comprising: a semiconductor substrate including a first conductivity type region of a first conductivity type, a first and second impurity regions of a second conductivity type provided in the first conductivity type region; a photoelectric converter located above the semiconductor substrate; and a first transistor including a gate electrode and at least a part of the second impurity region as a source or a drain. The first impurity region is at least partially located in a surface of the semiconductor substrate and electrically connected to the photoelectric converter. The second impurity region is electrically connected to the photoelectric converter via the first impurity region and has an impurity concentration lower than that of the first impurity region. The second impurity region at least partially overlaps the gate electrode in a plan view.

Abstract: An imaging device includes a semiconductor substrate comprising a first semiconductor; and a unit pixel cell provided to the semiconductor substrate. The unit pixel cell includes: a photoelectric converter that includes a pixel electrode and a photoelectric conversion layer, the photoelectric converter converting incident light into electric charges; a charge detection transistor that includes a part of the semiconductor substrate and detects the electric charges; and a reset transistor that includes at least a part of a first semiconductor layer comprising a second semiconductor and initializes a voltage of the photoelectric converter. The pixel electrode is located above the charge detection transistor. The reset transistor is located between the charge detection transistor and the pixel electrode. A band gap of the second semiconductor is larger than a band gap of the first semiconductor.

Abstract: An imaging device includes a semiconductor substrate; and a unit pixel cell provided to a surface of the semiconductor substrate. The unit pixel cell includes: a photoelectric converter that includes a pixel electrode and a photoelectric conversion layer located on the pixel electrode, the photoelectric converter converting incident light into electric charges; a charge detection transistor that includes a part of the semiconductor substrate and detects the electric charges; and a reset transistor that includes a first gate electrode and initializes a voltage of the photoelectric converter. The pixel electrode is located above the charge detection transistor. The reset transistor is located between the charge detection transistor and the pixel electrode. When viewed from a direction normal to the surface of the semiconductor substrate, the pixel electrode covers an entire portion of the first gate electrode.

Abstract: An imaging device includes a semiconductor substrate and at least one unit pixel cell provided to a surface of the semiconductor substrate. Each of the at least one unit pixel cell includes: a photoelectric converter including a pixel electrode and a photoelectric conversion layer located on the pixel electrode, the photoelectric converter converting incident light into electric charges; a charge detection transistor that includes a part of the semiconductor substrate and detects the electric charges; and a reset transistor that includes a gate electrode and initializes a voltage of the photoelectric converter. The pixel electrode is located above the charge detection transistor. The reset transistor is located between the charge detection transistor and the pixel electrode. When viewed from a direction normal to the surface of the semiconductor substrate, at least a part of the gate electrode is located outside the pixel electrode.

Abstract: A solid-state imaging device has a plurality of imaging-purpose pixels and a plurality of focus detection-purpose pixels. Each of the imaging-purpose pixels are provided with a first lower electrode, a photoelectric conversion film formed on the first lower electrode, and an upper electrode formed on the photoelectric conversion film. Each of the focus detection-purpose pixels is provided with a second lower electrode, the photoelectric conversion film formed on the second lower electrode, and the upper electrode formed on the photoelectric conversion film. The area of the second lower electrode is smaller than the area of the first lower electrodes. The second lower electrode is provided on a position deviating from a pixel center of a corresponding focus detection-pixel, and two second lower electrodes corresponding to two focus detection purpose pixels included in the plurality of focus detection purpose pixels is arranged in mutually opposite directions.

Abstract: Each unit pixel includes a photoelectric converter, an n-type impurity region forming an accumulation diode together with the semiconductor region, the accumulation diode accumulating a signal charge generated by the photoelectric converter, an amplifier transistor including a gate electrode electrically connected to the impurity region, and an isolation region formed around the amplifier transistor and implanted with p-type impurities. The amplifier transistor includes an n-type source/drain region formed between the gate electrode and the isolation region, and a channel region formed under the gate electrode. A gap in the isolation region is, in a gate width direction, wider at a portion including the channel region than at a portion including the source/drain region.

Abstract: Each unit pixel includes a photoelectric converter formed above a semiconductor region, an amplifier transistor formed in the semiconductor region, and including a gate electrode connected to the photoelectric converter, a reset transistor configured to reset a potential of the gate electrode, and an isolation region formed in the semiconductor region between the amplifier transistor and the reset transistor to electrically isolate the amplifier transistor from the reset transistor. The amplifier transistor includes a source/drain region. The source/drain region has a single source/drain structure.

Abstract: A solid-state imaging device includes unit pixels formed on a semiconductor substrate. Each of the unit pixels includes a photoelectric converter, a floating diffusion, a pinning layer, and a pixel transistor. The pixel transistor includes a gate electrode formed on the semiconductor substrate, a source diffusion layer, and a drain diffusion layer. At least one of the source diffusion layer or the drain diffusion layer functions as the floating diffusion. The pinning layer is covered by the floating diffusion at a bottom and a side at a channel of the pixel transistor. A conductivity type of the floating diffusion is opposite to that of the pinning layer.

Abstract: A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

Abstract: A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

Abstract: A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.