Patents by Inventor Kai Lin
Kai Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088025Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.Type: ApplicationFiled: November 27, 2023Publication date: March 14, 2024Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Tien-I Bao
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Publication number: 20240087224Abstract: A remote-control system, a remote-controller, and a remote-control method are provided. The remote-control method includes: obtaining environmental image data by an image capture device of a remote-controller; building a map according to the environmental image data based on simultaneous localization and mapping (SLAM) algorithm, and obtaining first location information of a first display in the map according to the environmental image data by the remote-controller; and receiving the first location information from the remote-controller and controlling the first display according to the first location information by a computing device.Type: ApplicationFiled: September 12, 2022Publication date: March 14, 2024Applicant: HTC CorporationInventors: Chun-Kai Huang, Jyun-Jhong Lin
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Publication number: 20240088562Abstract: An antenna structure includes a metal mechanism element, a feeding radiation element, a first radiation element, a second radiation element, a third radiation element, a fourth radiation element, a fifth radiation element, a sixth radiation element, and a tuning circuit. A slot is formed in the metal mechanism element. The first radiation element is coupled to the feeding radiation element. The tuning circuit is coupled to the first radiation element. The second radiation element is coupled to the feeding radiation element. The third radiation element is coupled to a first grounding point on the metal mechanism element. The fourth radiation element is coupled to a second grounding point on the metal mechanism element. The fifth radiation element is coupled to a third grounding point on the metal mechanism element.Type: ApplicationFiled: August 17, 2023Publication date: March 14, 2024Inventors: Guan-Ren SU, Meng-Kai WU, Hsieh-Chih LIN
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Patent number: 11927780Abstract: A dielectric grating apparatus comprises a substrate; a grating layer, disposed above the substrate; a first interference layer, disposed above the substrate; and a second interference layer, adjacent to the first interference layer, wherein a refractive index of a material of the second interference layer is greater than a refractive index of a material of the first interference layer.Type: GrantFiled: May 31, 2022Date of Patent: March 12, 2024Assignee: NATIONAL CHUNG SHAN INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Jian-Hung Lin, Chiang-Hsin Lin, Po-Tse Tai, Tsong-Dong Wang, Bo-Kai Feng
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Patent number: 11927799Abstract: A data transmission system is disclosed. The data transmission system includes at least one signal processing device, at least one conversion device, at least one antenna device, and at least one flexible printed circuit board. The at least one signal processing device is configured to generate or receive at least one data. The at least one conversion device is configured to transform between the at least one data and an optical signal. The at least one antenna device is configured to obtain the at least one data according to the optical signal, and configured to receive or transmit the at least one data wirelessly. The at least one flexible printed circuit board includes at least one conductive layer and at least one optical waveguide layer. The at least one optical waveguide layer is configured to transmit the optical signal.Type: GrantFiled: December 31, 2020Date of Patent: March 12, 2024Inventors: Po-Kuan Shen, Chun-Chiang Yen, Chiu-Lin Yu, Kai-Lun Han, Jenq-Yang Chang, Mao-Jen Wu, Chao-Chieh Hsu
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Patent number: 11929327Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.Type: GrantFiled: July 22, 2020Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Inc.Inventors: Hsu-Kai Chang, Keng-Chu Lin, Sung-Li Wang, Shuen-Shin Liang, Chia-Hung Chu
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Publication number: 20240079267Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first diffusion barrier layer made of a dielectric material including a metal element, nitrogen, and oxygen and a first protection layer made of a dielectric material including silicon and oxygen and in direct contact with the top surface of the first diffusion barrier layer. The semiconductor device structure also includes a first thickening layer made of a dielectric material including the metal element and oxygen and in direct contact with the top surface of the first protection layer. A maximum metal content in the first thickening layer is greater than that in the first diffusion barrier layer. The semiconductor device structure further includes a conductive feature surrounded by and in direct contact with the first diffusion barrier layer, the first protection layer, and the first thickening layer.Type: ApplicationFiled: November 9, 2023Publication date: March 7, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Cheng SHIH, Tze-Liang LEE, Jen-Hung WANG, Yu-Kai LIN, Su-Jen SUNG
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Patent number: 11923432Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.Type: GrantFiled: January 3, 2023Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yoh-Rong Liu, Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu, Li-Chi Yu, Sen-Hong Syue
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Patent number: 11923310Abstract: A package structure and method for forming the same are provided. The package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.Type: GrantFiled: August 9, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Kai Cheng, Tsung-Shu Lin, Tsung-Yu Chen, Hsien-Pin Hu, Wen-Hsin Wei
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Patent number: 11923255Abstract: Methods for manufacturing an electronic device are provided. A representative method includes providing a substrate. The substrate has an active layer, a first patterned metal layer passing through a passivation layer to electrically connected to the active layer, a second patterned metal layer passing through an insulating layer to electrically connected to the first patterned metal layer, and a metal layer under the second patterned metal layer. A part of the metal layer does not serve as a portion of a thin film transistor, and the part of the metal layer serves as a portion of a gate line. The method includes providing a carrier substrate supporting a plurality of elements, conducting a testing to the elements, transferring the elements from the carrier substrate to the second patterned metal layer of the substrate, and fixing the elements to the substrate.Type: GrantFiled: April 6, 2023Date of Patent: March 5, 2024Assignee: INNOLUX CORPORATIONInventors: Chia-Hsiung Chang, Ting-Kai Hung, Hsiao-Lang Lin
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Patent number: 11925002Abstract: A casing structure with functionality of effective thermal management is disclosed, which consists of a casing member, a low thermal conductivity medium, a second heat spreader, and a first heat spreader. When a user operates the electronic device, heat generated from CPU and/or GPU is transferred to the second heat spreader via the first heat spreader, and then is two-dimensionally spread in the second heat spreader. Consequently, the heat is dissipated away from the casing member to air due to the outstanding thermal radiation ability of the casing member. The low thermal conductivity medium is adopted for controlling a heat transfer of heat transferring paths from the heat source and ends to the casing member. By applying the casing structure in an electronic device by a form of a top casing and/or a back casing, an outer surface temperature of the casing member can be well controlled.Type: GrantFiled: February 16, 2021Date of Patent: March 5, 2024Assignee: AMLI MATERIALS TECHNOLOGY CO., LTD.Inventors: Jian-Jia Huang, Chun-Kai Lin, Chih-Ching Chen
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Publication number: 20240072299Abstract: A method of making solid oxidesolid oxide electrolyte membrane comprises steps (S1)-(S5). Step (S1), mixing a high molecular polymer and a first solvent to form a first mixed slurry; and homogenizing the first mixed slurry, to obtain a reagent A. Step (S2), mixing an oxide powder, a dispersant and a second solvent to form a second mixed slurry, treating the second mixed slurry, to obtain a reagent B. Step (S3), adding a protective agent into the reagent B to form a third mixed slurry, and homogenizing the third mixed slurry to obtain a reagent C. Step (S4), mixing the reagent A and the reagent C to form a fourth mixed slurry, and treating the fourth mixed slurry a fifth mixed slurry; and homogenizating the fifth mixed slurry to form a solid electrolyte slurry. And step (S5), producing the solid oxidesolid oxide electrolyte membrane by a coating process.Type: ApplicationFiled: April 12, 2023Publication date: February 29, 2024Inventors: HONG-ZHENG LAI, JING-KAI KAO, CHENG-TING LIN, TSENG-LUNG CHANG
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Publication number: 20240071804Abstract: Methods, systems, and assemblies suitable for gas-phase processes are disclosed. An exemplary assembly includes a susceptor ring and at least one injector tube. The injector tube can be disposed within the susceptor ring to provide a gas to a peripheral region of a substrate. Methods, systems, and assemblies can be used to obtain desired (e.g. composition and/or thickness) profiles of material on a substrate surface.Type: ApplicationFiled: August 28, 2023Publication date: February 29, 2024Inventors: Peipei Gao, Wentao Wang, Han Ye, Kai Zhou, Fan Gao, Xing Lin
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Publication number: 20240071504Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.Type: ApplicationFiled: August 30, 2022Publication date: February 29, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pei-Chun LIAO, Yu-Kai CHANG, Yi-Ching LIU, Yu-Ming LIN, Yih WANG, Chieh LEE
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Publication number: 20240066313Abstract: An electronic device includes a light emitting layer, a light conversion layer and an adjustable structure. The light emitting layer has a plurality of light emitting units for emitting light. The light conversion layer converts the wavelength of the light emitted by at least one light emitting unit to provide converted light. The adjustable structure is controlled to adjust a light penetrating area to correspond to the affected part to be treated, wherein at least one of the light and the converted light passes through the light penetrating area to irradiate the affected part.Type: ApplicationFiled: July 28, 2023Publication date: February 29, 2024Inventors: Jih-Ping LIN, Chun-Kai LEE, Fang-Iy WU, Cheng-Hsu CHOU
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Publication number: 20240061455Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.Type: ApplicationFiled: August 17, 2022Publication date: February 22, 2024Applicant: Vanguard International Semiconductor CorporationInventors: Shao-Chang HUANG, Yeh-Ning JOU, Ching-Ho LI, Kai-Chieh HSU, Chun-Chih CHEN, Chien-Wei WANG, Gong-Kai LIN, Li-Fan CHEN
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Patent number: 11904519Abstract: Present invention is related to an extrusion equipment for processing a fibre composite. The extrusion equipment comprises a decompression and a melt tank arranged and operated vertically along with the direction of gravity. The melt tank comprises a melt tank impregnation section and a melt tank control section with a melt tank cavity as a channel condition defined within. The channel has its inner diameter or passage gradually decreased from top to bottom. The extrusion equipment provided by the present invention is configured in the direction of gravity for processing the melted thermoplastic resin and the fibre vertically for avoiding fibre fracture or breakage and improving the quality of the final products. As the melted plastic is processed vertically along with the gravity, the melted plastic could transfer or pass through the channel quickly without resulting decomposition due to the high heat and the long retention time in the cavity.Type: GrantFiled: April 7, 2022Date of Patent: February 20, 2024Assignee: Plastics Industry Development CenterInventors: Chia-Yu Yu, Li-Kai Lin, Chia-Hsin Tung, Wei-Cheng Chen
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Publication number: 20240054635Abstract: Provided are a vibration object monitoring method and apparatus, a computer device, and a storage medium. The method includes: in response to detecting that a vibration object exists in a monitoring video picture for a target monitoring region, a vibration object region in the monitoring video picture is determined, where the vibration object region is a region where the vibration object is located in the monitoring video picture; displacement information of a key point of the vibration object in the vibration object region is recorded; vibration information of the vibration object in the monitoring video picture is determined based on the displacement information; and a vibration object monitoring result for the target monitoring region is generated according to the vibration information. The abnormal vibration monitoring can be performed on the vibration object in the target monitoring region in time according to this method.Type: ApplicationFiled: March 8, 2021Publication date: February 15, 2024Applicant: CSG POWER GENERATION CO., LTD.Inventors: Yumin PENG, Zhiqiang WANG, Hao ZHANG, Hengjun CHEN, Xun HU, Tuixiang FENG, Liqun SUN, Man CHEN, Yong LU, Tao LIU, Kai LIN, Yulin HAN
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Publication number: 20240055806Abstract: An electrical connector includes: plural terminal modules each including a row of terminals arranged in a first direction and an insulator molded with the row of terminals, the plural terminal modules being arranged in a second direction perpendicular to the first direction; and an insulating housing overmolding and retaining the plurality of terminal modules to define a mating cavity, wherein the insulator of each terminal module defines plural through holes running therethrough in the second direction, and materials of the insulating housing fill the through holes of each terminal module.Type: ApplicationFiled: August 9, 2023Publication date: February 15, 2024Inventors: SHIH-KAI LIN, CHIN-JUNG WU, MING-CHUAN WU
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Patent number: 11901439Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.Type: GrantFiled: July 27, 2022Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu