Abstract: A waveguide structure includes a dielectric layer, a plurality of circuit layers, a plurality of insulation layers, and a conductor connection layer. The dielectric layer has an opening. The circuit layers are disposed on the dielectric layer. The insulation layers and the circuit layers are alternately stacked. The conductor connection layer covers an outer wall of the opening in a direction perpendicular to the circuit layers and connects at least two circuit layers on two opposite sides of the opening. At least the conductor connection layer and a part of the circuit layers define an air cavity for transmitting signals at a position corresponding to the opening.

Abstract: Compounds, particles, and cathode active materials that can be used in lithium ion batteries are described herein. Methods of making such compounds, powders, and cathode active materials are described.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

Abstract: A gait activity learning assistance system, and an application method thereof, includes a main body, at least one movement detecting module, a control module, at least one driving module and at least one dynamic measurement module. The system is able to guide and induce a user to learn gait autonomously by disposing at least one force-transmission unit on at least one limb position of the user, besides, the system is able to measure a dynamic change of the at least one force-transmission unit by the at least one dynamic measurement module while user receiving a gait assistance, and send them back to the control module immediately for a real-time analysis.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.

Abstract: A semiconductor structure including a substrate, a first dielectric layer, a first conductive feature, an etch stop layer, a second dielectric layer and a second conductive feature is provided. The first dielectric layer is disposed over the substrate. The first conductive feature is disposed in the first dielectric layer. The etch stop layer is disposed over the first dielectric layer and the first conductive feature, wherein the etch stop layer comprises a metal-containing layer and a silicon-containing layer, the metal-containing layer is located between the first dielectric layer and the silicon-containing layer, the metal-containing layer comprises a nitride-containing region and an oxide-containing region, and the nitride-containing region contacts the first conductive feature. The second dielectric layer is disposed over the etch stop layer. The second conductive feature penetrates the second dielectric layer and electrically connects with the first conductive feature.

Abstract: Some implementations described herein provide techniques and apparatuses for a semiconductor processing tool including an electrostatic chuck having a voltage-regulation system to regulate an electrical potential throughout regions of a semiconductor substrate positioned above the electrostatic chuck. The voltage-regulation system may determine that an electrical potential within a region of the semiconductor substrate does not satisfy a threshold. The voltage-regulation system may, based on determining that the electrical potential throughout the region does not satisfy the threshold, position one or more electrically-conductive pins within the region. While positioned within the region, the one or more electrically-conductive pins may change the electrical potential of the region.

Abstract: Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell along with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.

Abstract: A machine learning method comprises: (a) applying a contrastive learning model to a training image and an image mask to generate a foreground feature vector pair and a background feature vector pair; (b) calculating a foreground loss and a background loss according to the foreground feature vector pair and the background feature vector pair; (c) calculating a total loss from the foreground loss and the background loss; (e) when a recursion end condition is met, using a first encoder for parameter adjustment of machine learning model; and (f) when the recursive end condition is not met, adjusting a parameter of the first encoder in the contrastive learning model using the total loss, and adjust a parameter of a second encoder in the contrastive learning model using the adjusted parameter of the first encoder and a preset multiple, thereby performing step (a) to step (d) again.

Abstract: Semiconductor devices including air gaps between source/drain regions and a semiconductor substrate and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region on the semiconductor substrate; a gate structure on the first channel region; a first source/drain region adjacent the gate structure and the first channel region; a first inner spacer layer between the first source/drain region and the semiconductor substrate in a first direction perpendicular to a major surface of the semiconductor substrate; and a first air gap between the first source/drain region and the first inner spacer layer in the first direction.

Abstract: A method includes forming a stack of layers comprising a plurality of semiconductor nanostructures, and a plurality of sacrificial layers. The plurality of semiconductor nanostructures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, depositing a first spacer layer extending into the lateral recesses, with the first spacer layer comprising a first dielectric material, depositing a second spacer layer on the first spacer layer, with the second spacer layer comprising a second dielectric material different from the first dielectric material, and trimming the first spacer layer and the second spacer layer to form inner spacers.

Abstract: Semiconductor devices and methods of manufacture are presented herein in which a etch stop layer is selectively deposited over a conductive contact. A dielectric layer is formed over the etch stop layer and an opening is formed through the dielectric layer and the etch stop layer to expose the conductive contact. Conductive material is then deposited to fill the opening.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, first and second deep well regions, and first and second well regions disposed in the semiconductor substrate. The second deep well region is located above the first deep well region. The first well region is located above the first deep well region. The second well region is located above the second deep well region. A conductivity type of the second deep well region is complementary to that of the first deep well region. A conductivity type of the second well region is complementary to that of the first well region and the second deep well region. A length of the second deep well region is greater than or equal to that of the second well region and less than that of the first deep well region. The first well region is connected with the first deep well region.

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.

Abstract: A Mg—Li—Al—Zn alloy is disclosed. The Mg—Li—Al—Zn alloy comprises, in weight percent: 5-15% Li, 1.5-9.0% Al, 0.5-1.5% Zn, 0.4-1.3% Y, 0.18-1.01% Nd, 0.09-0.65% Ce, and the balance Mg and incidental impurities. Experimental data have proved that, this novel Mg—Li—Al—Zn alloy has a flashover temperature in a range between 620° C. and 700° C., such that the flashover temperature of the specifically-designed Mg—Li—Al—Zn alloy is greater than that of commercial LAZ521, LAZ721, LAZ771, LAZ921, and LAZ1491 alloys. Therefore, the Mg—Li—Al—Zn alloy of the present invention can be processed to be a structural article through air melt and casting process.

Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.

Abstract: A three-dimensional object reconstruction method, applied to a terminal device or a server, is provided. The method includes obtaining a plurality of video frames of an object; determining three-dimensional location information of key points of the object in the plurality of video frames and physical meaning information of the key points, the physical meaning information indicating respective positions of the object; determining a correspondence between the key points having the same physical meaning information in the plurality of video frames; and generating a three-dimensional object according to the correspondence and the three-dimensional location information of the key points.

Abstract: A method of fabricating a metal gate transistor includes providing a substrate. Then, a high-k dielectric layer is formed to cover the substrate. Later, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. After the ion implantation process, a polysilicon gate is formed on the high-k dielectric layer. Next, an interlayer dielectric layer is formed to cover the substrate and the polysilicon gate. Finally, the polysilicon gate is replaced by a metal gate.

Abstract: A key structure is stacked on a display panel. The key structure includes a trigger plate, a frame, at least an elastic triggering member, and at least a key. The trigger plate is formed with at least a hollow area for the display panel to partially expose and a solid area. The frame is disposed on the trigger plate and is formed with at least an opening opposite the hollow area. The key includes a key cap and a scissor member connected to the key cap, wherein the key cap has a cap body which is located in the opening and helps directly observing the hollow area and at least two skirts which extend from sides of the cap body and are covered by the frame.

Abstract: A carbon-coated cathode material and a preparation method thereof. The carbon-coated cathode material includes a lithium metal phosphate particle and a carbon coating layer. The carbon coating layer is coated on the lithium metal phosphate particle. The carbon coating layer is formed by a first heat treatment and a second heat treatment. A first carbon source is added in the first heat treatment, and a second carbon source is added in the second heat treatment. The first carbon source has a first weight percentage relative to the lithium metal phosphate particle. The second carbon source has a second weight percentage relative to the lithium metal phosphate particle. The first weight percentage of the first carbon source is equal to or less than the second weight percentage of the second carbon source.