Patents by Inventor Kai-Ming Ching
Kai-Ming Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230230935Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.Type: ApplicationFiled: March 21, 2023Publication date: July 20, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Ching, Shu-Shen Yeh, Chien-Hung Chen, Hui-Chang Yu, Yu-Min Cheng
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Patent number: 11637072Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.Type: GrantFiled: March 16, 2021Date of Patent: April 25, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Ching, Shu-Shen Yeh, Chien-Hung Chen, Hui-Chang Yu, Yu-Min Cheng
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Publication number: 20220148979Abstract: A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.Type: ApplicationFiled: March 16, 2021Publication date: May 12, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Ching, Shu-Shen Yeh, Chien-Hung Chen, Hui-Chang Yu, Yu-Min Cheng
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Patent number: 9859252Abstract: An integrated circuit structure includes a die including a semiconductor substrate, dielectric layers over the semiconductor substrate, an interconnect structure including metal lines and vias in the dielectric layers, a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers, and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.Type: GrantFiled: May 27, 2016Date of Patent: January 2, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Ching, Ching-Wen Hsiao, Tsung-Ding Wang, Ming Hung Tseng, Chen-Shien Chen
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Patent number: 9673174Abstract: System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.Type: GrantFiled: January 13, 2015Date of Patent: June 6, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Ding Wang, Chen-Shien Chen, Kai-Ming Ching, Bo-I Lee, Chien-Hsun Lee
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Publication number: 20160276314Abstract: An integrated circuit structure includes a die including a semiconductor substrate, dielectric layers over the semiconductor substrate, an interconnect structure including metal lines and vias in the dielectric layers, a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers, and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.Type: ApplicationFiled: May 27, 2016Publication date: September 22, 2016Inventors: Kai-Ming Ching, Ching-Wen Hsiao, Tsung-Ding Wang, Ming Hung Tseng, Chen-Shien Chen
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Patent number: 9355933Abstract: An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.Type: GrantFiled: December 18, 2013Date of Patent: May 31, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Ching, Ching-Wen Hsiao, Tsung-Ding Wang, Ming Hung Tseng, Chen-Shien Chen
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Patent number: 9236359Abstract: A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit.Type: GrantFiled: April 13, 2015Date of Patent: January 12, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Kai-Ming Ching
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Publication number: 20150214166Abstract: A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit.Type: ApplicationFiled: April 13, 2015Publication date: July 30, 2015Inventor: Kai-Ming Ching
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Publication number: 20150137328Abstract: System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.Type: ApplicationFiled: January 13, 2015Publication date: May 21, 2015Inventors: Dean Wang, Chen-Shien Chen, Kai-Ming Ching, Bo-I Lee, Chien-Hsiun Lee
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Patent number: 9006892Abstract: A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit.Type: GrantFiled: November 12, 2012Date of Patent: April 14, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Kai-Ming Ching
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Patent number: 8932906Abstract: System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.Type: GrantFiled: August 19, 2008Date of Patent: January 13, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Dean Wang, Chen-Shien Chen, Kai-Ming Ching, Bo-I Lee, Chien-Hsiun Lee
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Patent number: 8703609Abstract: A method of fabricating a semiconductor device including providing a substrate having a front surface and a back surface. A masking element is formed on the front surface of the substrate. The masking element includes a first layer having a first opening and a second layer having a second opening of a greater width than the first opening. The second opening is a tapered opening. The method further includes etching a tapered profile via extending from the front surface to the back surface of the substrate using the formed masking element.Type: GrantFiled: July 1, 2011Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Cheng Kuo, Chen Chen-Shien, Kai-Ming Ching, Chih-Hua Chen
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Publication number: 20140103540Abstract: An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.Type: ApplicationFiled: December 18, 2013Publication date: April 17, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Ching, Ching-Wen Hsiao, Tsung-Ding Wang, Ming Hung Tseng, Chen-Shien Chen
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Patent number: 8670637Abstract: An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.Type: GrantFiled: August 12, 2011Date of Patent: March 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Cheng Chang, Jin-Lien Lin, Kuo-Ching Hsu, Kai-Ming Ching, Jiun Yi Wu, Yen-Huei Chen
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Patent number: 8624360Abstract: An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.Type: GrantFiled: November 11, 2009Date of Patent: January 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Ching, Ching-Wen Hsiao, Tsung-Ding Wang, Ming-Hong Tseng, Chen-Shien Chen
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Patent number: 8497584Abstract: A new method is provided for the creation of a solder bump. Conventional methods are initially followed, creating a patterned layer of Under Bump Metal over the surface of a contact pad. A layer of photoresist is next deposited, this layer of photoresist is patterned and developed creating a resist mask having a T-shape opening aligned with the contact pad. This T-shaped opening is filled with a solder compound, creating a T-shaped layer of solder compound on the surface of the layer of UBM. The layer of photoresist is removed, exposing the created T-shaped layer of solder compound, further exposing the layer of UBM. The layer of UBM is etched using the T-shaped layer of solder compound as a mask. Reflow of the solder compound results in creating a solder ball.Type: GrantFiled: March 26, 2004Date of Patent: July 30, 2013Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yen-Ming Chen, Chia-Fu Lin, Shun-Liang Hsu, Kai-Ming Ching, Hsin-Hui Lee, Chao-Yuan Su, Li-Chih Chen
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Patent number: 8476769Abstract: An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a substrate; a through-silicon via (TSV) extending into the substrate; a TSV pad spaced apart from the TSV; and a metal line over, and electrically connecting, the TSV and the TSV pad.Type: GrantFiled: October 17, 2007Date of Patent: July 2, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hua Chen, Chen-Shien Chen, Chen-Cheng Kuo, Kuo-Ching “Steven” Hsu, Kai-Ming Ching
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Patent number: 8456008Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.Type: GrantFiled: September 15, 2011Date of Patent: June 4, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Cheng Kuo, Kai-Ming Ching, Chen Chen-Shien
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Patent number: 8426256Abstract: A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer.Type: GrantFiled: February 5, 2010Date of Patent: April 23, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: C. W. Hsiao, Bo-I Lee, Tsung-Ding Wang, Kai-Ming Ching, Chen-Shien Chen, Chien-Hsiun Lee, Clinton Chao