Patents by Inventor Kai-Ming Ching
Kai-Ming Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8309396Abstract: A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit.Type: GrantFiled: November 12, 2009Date of Patent: November 13, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Kai-Ming Ching
-
Patent number: 8097953Abstract: A system, a structure and a method of manufacturing stacked semiconductor substrates is presented. A first substrate includes a first side and a second side. A through substrate via (TSV) protrudes from the first side of the first substrate. A first protruding portion of the TSV has a conductive protective coating and a second protruding portion of the TSV has an isolation liner. The system further includes a second substrate and a joint interface structure that bonds the second substrate to the first substrate at the conductive protective coating of the first protruding portion of the TSV.Type: GrantFiled: October 28, 2008Date of Patent: January 17, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Hong Tseng, Kai-Ming Ching, Chen-Shien Chen, Ching-Wen Hsiao, Hon-Lin Huang, Tsung-Ding Wang
-
Publication number: 20120001334Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.Type: ApplicationFiled: September 15, 2011Publication date: January 5, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Cheng Kuo, Kai-Ming Ching, Chen Chen-Shien
-
Publication number: 20110299809Abstract: An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.Type: ApplicationFiled: August 12, 2011Publication date: December 8, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Cheng Chang, Jin-Lien Lin, Kuo-Ching Hsu, Kai-Ming Ching, Jiun Yi Wu, Yen-Huei Chen
-
Publication number: 20110263120Abstract: A method of fabricating a semiconductor device including providing a substrate having a front surface and a back surface. A masking element is formed on the front surface of the substrate. The masking element includes a first layer having a first opening and a second layer having a second opening of a greater width than the first opening. The second opening is a tapered opening. The method further includes etching a tapered profile via extending from the front surface to the back surface of the substrate using the formed masking element.Type: ApplicationFiled: July 1, 2011Publication date: October 27, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Cheng Kuo, Chen Chen-Shien, Kai-Ming Ching, Chih-Hua Chen
-
Patent number: 8034708Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.Type: GrantFiled: October 22, 2010Date of Patent: October 11, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Cheng Kuo, Kai-Ming Ching, Chen-Shien Chen
-
Patent number: 8005326Abstract: An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via.Type: GrantFiled: July 10, 2008Date of Patent: August 23, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Cheng Chang, Jin-Lien Lin, Kuo-Ching Hsu, Kai-Ming Ching, Jiun Yi Wu, Yen-Huei Chen
-
Patent number: 7973413Abstract: A semiconductor device including a substrate having a front surface and a back surface is provided. A plurality of interconnect layers are formed on the front surface and have a first surface opposite the front surface of the substrate. A tapered profile via extends from the first surface of the plurality of interconnect layers to the back surface of the substrate. In one embodiment, a insulating layer is formed on the substrate and includes an opening, and wherein the opening includes conductive material providing contact to the tapered profile via.Type: GrantFiled: August 24, 2007Date of Patent: July 5, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Cheng Kuo, Chen Chen-Shien, Kai-Ming Ching, Chih-Hua Chen
-
Patent number: 7906425Abstract: A process including providing a semiconductor device including a bond pad, and an under bump metallurgy overlying the bond pad. Forming a solder structure over the under bump metallurgy, and wherein the solder structure includes an outer layer including tin oxide. Producing a plasma from at least one of CF4 and SF6, and exposing the solder structure to the plasma. Heating the solder structure and cooling the same to provide a solder bump on the semiconductor device.Type: GrantFiled: October 13, 2006Date of Patent: March 15, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen, Wen-Chang Kuo, Yue-Ying Jian
-
Patent number: 7888236Abstract: A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas.Type: GrantFiled: May 14, 2007Date of Patent: February 15, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Ping Pu, Bai-Yao Lou, Dean Wang, Ching-Wen Hsiao, Kai-Ming Ching, Chen-Cheng Kuo, Wen-Chih Chiou, Ding-Chung Lu, Shang-Yun Hou
-
Publication number: 20110034027Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.Type: ApplicationFiled: October 22, 2010Publication date: February 10, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Cheng Kuo, Kai-Ming Ching, Chen Chen-Shien
-
Patent number: 7843064Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.Type: GrantFiled: May 14, 2008Date of Patent: November 30, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Cheng Kuo, Kai-Ming Ching, Chen Chen-Shien
-
Publication number: 20100279463Abstract: A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer.Type: ApplicationFiled: February 5, 2010Publication date: November 4, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: C. W. Hsiao, Bo-l Lee, Tsung-Ding Wang, Kai-Ming Ching, Chen-Shien Chen, Chien-Hsiun Lee, Clinton Chao
-
Patent number: 7816227Abstract: An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV.Type: GrantFiled: June 30, 2009Date of Patent: October 19, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Shien Chen, Chen-Cheng Kuo, Kai-Ming Ching, Chih-Hua Chen
-
Patent number: 7785927Abstract: A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration.Type: GrantFiled: February 25, 2009Date of Patent: August 31, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Shien Chen, Kai-Ming Ching, Chih-Hua Chen, Chen-Cheng Kuo
-
Publication number: 20100187684Abstract: A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit.Type: ApplicationFiled: November 12, 2009Publication date: July 29, 2010Inventor: Kai-Ming Ching
-
Publication number: 20100117201Abstract: An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.Type: ApplicationFiled: November 11, 2009Publication date: May 13, 2010Inventors: Kai-Ming Ching, Ching-Wen Hsiao, Tsung-Ding Wang, Ming-Hong Tseng, Chen-Shien Chen
-
Publication number: 20100102453Abstract: A system, a structure and a method of manufacturing stacked semiconductor substrates is presented. A first substrate includes a first side and a second side. A through substrate via (TSV) protrudes from the first side of the first substrate. A first protruding portion of the TSV has a conductive protective coating and a second protruding portion of the TSV has an isolation liner. The system further includes a second substrate and a joint interface structure that bonds the second substrate to the first substrate at the conductive protective coating of the first protruding portion of the TSV.Type: ApplicationFiled: October 28, 2008Publication date: April 29, 2010Inventors: Ming-Hong Tseng, Kai-Ming Ching, Chen-Shien Chen, Ching-Wen Hsiao, Hon-Lin Huang, Tsung-Ding Wang
-
Publication number: 20100047963Abstract: System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.Type: ApplicationFiled: August 19, 2008Publication date: February 25, 2010Inventors: Dean Wang, Chen-Shien Chen, Kai-Ming Ching, Bo-I Lee, Chien-Hsiun Lee
-
Patent number: 7666688Abstract: A method of manufacturing a coil inductor and a coil inductor are provided. A plurality of conductive bottom structures are formed to be lying on a first dielectric layer. A plurality pairs of conductive side structures are then formed, wherein each pair of the conductive side structure stand on top surface of a first end and a second end of each conductive bottom structure respectively; a second dielectric layer is formed on the first dielectric layer, coating the bottom and side structures; and a plurality of conductive top structures are formed to be lying on the second dielectric layer, wherein each conductive top structure electrically connects each pair of the conductive side structures, wherein the conductive bottom structures, the conductive side structures and the conductive top structures together form a conductive coil structure.Type: GrantFiled: January 25, 2008Date of Patent: February 23, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Ming Ching, Chen-Shien Chen