Patents by Inventor Kai-Ming Ching

Kai-Ming Ching has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030134496
    Abstract: A method of forming a bump on a substrate such as a semiconductor wafer or flip chip. The method includes the act of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. An electrically conductive redistribution trace is deposited over the under bump metallurgy. A photoresist layer is deposited, patterned and developed to provide portions selectively protecting the electrically conductive redistribution trace and the under bump metallurgy. Excess portions of the electrically conductive redistribution trace and under bump metallurgy not protected by the photoresist are removed.
    Type: Application
    Filed: January 12, 2002
    Publication date: July 17, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Hui Lee, Chia-Fu Lin, Chao-Yuan Su, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen
  • Publication number: 20030133115
    Abstract: A method including the acts of providing a semiconductor device having a plurality of misalignment ruler markers formed therein for measuring removable layer opening misalignment in the X and Y directions, a bond pad and the passivation layer with an opening therein down to the bond pad. A removable layer is formed over the semiconductor device and includes an opening therein down to the bond pad. Preferably this action includes depositing, patterning and developing a dry photoresist film layer over the semiconductor device with an opening therein down to the bond pad. The next act includes measuring the misalignment of the opening in the passivation layer by counting the number of misalignment ruler markers visibly exposed by the opening in the X-direction and also the Y-direction.
    Type: Application
    Filed: January 12, 2002
    Publication date: July 17, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Chen, Chia-Fu Lin, Kai-Ming Ching, Chao-Yuan Su, Hsin-Hui Lee, Li-Chih Chen
  • Publication number: 20030134233
    Abstract: A method for protecting a semiconductor process wafer surface from contacting thermally degraded photoresist including providing a semiconductor process wafer having a process surface; forming a protective layer over selected areas of the process surface said protective layer including a resinous organic material having a glass transition temperature (Tg) that is about greater than a thermal treatment temperature; forming a photoresist layer over at least a portion of the protective layer to include a photolithographic patterning process; and subjecting the semiconductor process wafer to the thermal treatment temperature.
    Type: Application
    Filed: January 16, 2002
    Publication date: July 17, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Yuan Su, Chia-Fu Lin, Hsin-Hui Lee, Yen-Ming Chen, Kai-Ming Ching, Li-Chih Chen
  • Publication number: 20030124832
    Abstract: A method of forming a bump on a substrate such as a semiconductor wafer or flip chip without producing metal ribbon residue. The method includes the step of providing a semiconductor device having a contact pad and having an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. A photoresist layer is deposited over the under bump metallurgy. The photoresist layer is a dry film photoresist. The photoresist layer is patterned to provide an opening in the photoresist layers down to the under bump metallurgy and aligned with the contact pad. Additional energy is applied to the photoresist layer to improve the adhesion of the photoresist layer to the under bump metallurgy. An electrically conductive material is deposited into the opening formed in the photoresist layers and overlying the under bump metallurgy and aligned with contact pad.
    Type: Application
    Filed: December 31, 2001
    Publication date: July 3, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hsin Tseng, Hsiu-Mei Yu, Ta-Yang Lin, Fang-Chung Liu, Kai-Ming Ching, Tung-Heng Shie
  • Publication number: 20020064729
    Abstract: Within both a method for forming a patterned photoresist layer and a method for forming an electroplated patterned conductor layer while employing the patterned photoresist layer as a patterned photoresist plating mask layer there is first provided a substrate. There is then formed over the substrate a blanket photoresist layer formed of a negative photoresist material. There is then photoexposed the blanket photoresist layer to form a photoexposed blanket photoresist layer while employing a photoexposure apparatus which employs an annular edge ring exclusion apparatus positioned over an annular edge ring of the blanket photoresist layer and the substrate. Finally, there is then developed the photoexposed blanket photoresist layer to form a patterned photoresist layer having an annular edge ring excluded over the annular edge ring of the substrate.
    Type: Application
    Filed: November 30, 2000
    Publication date: May 30, 2002
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Ming Ching, Sheng-Liang Pan, Hao-Wei Chang, Chun-Hong Chang, Yen-Ming Chen