Patents by Inventor Kambiz Kaviani
Kambiz Kaviani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220350390Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: ApplicationFiled: May 19, 2022Publication date: November 3, 2022Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
-
Patent number: 11340686Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: GrantFiled: August 26, 2020Date of Patent: May 24, 2022Assignee: Rambus Inc.Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
-
Publication number: 20210041932Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: ApplicationFiled: August 26, 2020Publication date: February 11, 2021Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
-
Patent number: 10761587Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: GrantFiled: November 16, 2018Date of Patent: September 1, 2020Assignee: Rambus Inc.Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
-
Publication number: 20200232028Abstract: Provided herein are devices and methods suitable for sequencing, amplifying, analyzing, and performing sample preparation procedures for nucleic acids and other biomolecules.Type: ApplicationFiled: January 7, 2020Publication date: July 23, 2020Inventors: Hesaam Esfandyarpour, Hamid Rategh, Meysam R. Barmi, Kosar B. Parizi, Kambiz Kaviani
-
Patent number: 10570449Abstract: Provided herein are devices and methods suitable for sequencing, amplifying, analyzing, and performing sample preparation procedures for nucleic acids and other biomolecules.Type: GrantFiled: October 5, 2017Date of Patent: February 25, 2020Assignee: GENAPSYS, INC.Inventors: Hesaam Esfandyarpour, Hamid Rategh, Meysam R. Barmi, Kosar B. Parizi, Kambiz Kaviani
-
Publication number: 20190171272Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: ApplicationFiled: November 16, 2018Publication date: June 6, 2019Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
-
Patent number: 10133338Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: GrantFiled: May 8, 2017Date of Patent: November 20, 2018Assignee: Rambus Inc.Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
-
Publication number: 20180155780Abstract: Provided herein are devices and methods suitable for sequencing, amplifying, analyzing, and performing sample preparation procedures for nucleic acids and other biomolecules.Type: ApplicationFiled: October 5, 2017Publication date: June 7, 2018Inventors: Hesaam Esfandyarpour, Hamid Rategh, Meysam R. Barmi, Kosar B, Parizi, Kambiz Kaviani
-
Patent number: 9809852Abstract: Provided herein are devices and methods suitable for sequencing, amplifying, analyzing, and performing sample preparation procedures for nucleic acids and other biomolecules.Type: GrantFiled: March 14, 2014Date of Patent: November 7, 2017Assignee: GENAPSYS, INC.Inventors: Hesaam Esfandyarpour, Hamid Rategh, Meysam R. Barmi, Kosar B. Parizi, Kambiz Kaviani
-
Publication number: 20170308144Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: ApplicationFiled: May 8, 2017Publication date: October 26, 2017Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
-
Patent number: 9645631Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: GrantFiled: August 26, 2016Date of Patent: May 9, 2017Assignee: Rambus Inc.Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
-
Patent number: 9606223Abstract: An electronic device for wirelessly tracking the position of a second electronic device is disclosed. The electronic device includes transceiver circuitry having a beacon generator to generate a beacon at a particular frequency and direction. An antenna array transmits the beacon, and receives at least one reflected beacon from the second electronic device. The reflected beacon is received if a position of the second electronic device lies within a range of directions of the beacon. The transceiver circuitry further includes an injection-locked oscillator having an input coupled to the antenna array to receive reflected beacons, and to lock to the reflected beacon when the reflected beacon has a frequency value within locking range of the oscillator. Processing circuitry coupled to the transceiver circuitry tracks the position of the second device based on the lock condition of the oscillator.Type: GrantFiled: August 1, 2012Date of Patent: March 28, 2017Assignee: Lattice Semiconductor CorporationInventors: Farshid Aryanfar, Marko Aleksić, Kambiz Kaviani
-
Publication number: 20170052584Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: ApplicationFiled: August 26, 2016Publication date: February 23, 2017Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
-
Patent number: 9571034Abstract: Coupled multi-inductors and their applications. An apparatus includes several circuit stages. Each circuit stage includes an inductive element that overlaps with the inductive elements of its adjacent circuit stages, forming a loop of coupled circuit stages. The apparatus may be, for example, a multi-phase oscillator with multiple oscillators that are magnetically coupled to each other for generating oscillation signals at different phases. The apparatus may also be, for example, a phase interpolator for combining input signals.Type: GrantFiled: February 22, 2016Date of Patent: February 14, 2017Assignee: Rambus Inc.Inventors: Mohammad Hekmat, Farshid Aryanfar, Kambiz Kaviani
-
Patent number: 9564879Abstract: A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.Type: GrantFiled: September 15, 2015Date of Patent: February 7, 2017Assignee: Rambus Inc.Inventors: Lei Luo, Barry W. Daly, Kambiz Kaviani, John Cronan Eble, III, John Wilson
-
Patent number: 9515856Abstract: A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.Type: GrantFiled: May 22, 2015Date of Patent: December 6, 2016Assignee: Rambus Inc.Inventors: Kambiz Kaviani, Amir Amirkhany, Jason Chia-Jen Wei, Aliazam Abbasfar
-
Patent number: 9431089Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.Type: GrantFiled: June 10, 2013Date of Patent: August 30, 2016Assignee: Rambus Inc.Inventors: Dinesh Patil, Amir Amirkhany, Farrukh Aquil, Kambiz Kaviani, Frederick A. Ware
-
Patent number: 9432227Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.Type: GrantFiled: December 18, 2014Date of Patent: August 30, 2016Assignee: Rambus Inc.Inventors: Amir Amirkhany, Kambiz Kaviani, Aliazam Abbasfar
-
Publication number: 20160241191Abstract: Coupled multi-inductors and their applications. An apparatus includes several circuit stages. Each circuit stage includes an inductive element that overlaps with the inductive elements of its adjacent circuit stages, forming a loop of coupled circuit stages. The apparatus may be, for example, a multi-phase oscillator with multiple oscillators that are magnetically coupled to each other for generating oscillation signals at different phases. The apparatus may also be, for example, a phase interpolator for combining input signals.Type: ApplicationFiled: February 22, 2016Publication date: August 18, 2016Inventors: Mohammad Hekmat, Farshid Aryanfar, Kambiz Kaviani