Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.

Abstract: A source-synchronous communication system in which a first integrated circuit (IC) conveys a data signal and concomitant strobe signal to a second IC. One or both ICs support hysteresis for the strobe channel that allows the second IC to distinguish between strobe preambles and noise, and thus prevent the false triggering of data capture. Hysteresis may also be employed to quickly settle the strobe channel to an inactive level after receipt of a strobe postamble.

Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

Abstract: Coupled multi-inductors and their applications. An apparatus includes several circuit stages. Each circuit stage includes an inductive element that overlaps with the inductive elements of its adjacent circuit stages, forming a loop of coupled circuit stages. The apparatus may be, for example, a multi-phase oscillator with multiple oscillators that are magnetically coupled to each other for generating oscillation signals at different phases. The apparatus may also be, for example, a phase interpolator for combining input signals.

Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.

Abstract: The common-mode input voltage of a common-gate input amplifier receiving a differential signal is set in an open-loop manner by basing the bias current and/or source load impedances of the common-gate amplifier on a transmitter bias current and driving impedance. The common-mode input voltage of a common-gate input amplifier receiving a differential signal may be set in a closed-loop manner using a feedback loop having a captured target voltage compared to the common-mode input voltage at a node of the amplifier. The common-mode input voltage of a common-gate input amplifier receiving a differential signal may be set in a continuous time closed loop manner by sending a reference current through resistances that are multiples of a resistance used to generate the reference current.

Abstract: Provided herein are devices and methods suitable for sequencing, amplifying, analyzing, and performing sample preparation procedures for nucleic acids and other biomolecules.

Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

Abstract: A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.

Abstract: Encoder and decoder circuits that encode and decode a series of data words to/from a series of code words. The data words include L symbols. The code words include M symbols, where M is larger than L. A set of tightly coupled M links to convey respective symbols in each of the series of code words. The code words are selected such that between every two consecutive code words in a series of code words, an equal number of transitions from low to high and high to low occur on a subset of the M-links.

Abstract: A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.

Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.

Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

Abstract: A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

Abstract: A transceiver includes a transmitter and receiver that form a series current path between two power-supply nodes. Powering both the transmitter and receiver with the same supply current saves power. The transmitter functions as a resistive load for the receiver, and thus performs useful work with power that would otherwise be dissipated as waste heat.

Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.

Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.

Abstract: Differential receivers are “stacked” and independently calibrated to different common-mode voltages. The different common-mode voltages may correspond to the common-mode voltages of stacked transmission circuits. Multiple stacks of samplers are connected to the same channels. The clocking of each stack of sampler circuits is phased (timed) such that the samplers in a given stack are not resolving at the same time. Samplers in a different stack and receiving a different common-mode voltage resolve at the same time.

Abstract: A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.