Abstract: The disclosed embodiments relate to the design of a linear equalizer that supports low-power, high-speed data transfers. In some embodiments, this linear equalizer contains a passive network that provides selective frequency peaking in a frequency range associated with a falling edge of a frequency response of the channel. It also includes a level shifter coupled between the channel and the passive network, wherein the level shifter is an active component that provides amplification and/or level-shifting. Moreover, the linear equalizer is designed so that power from the level shifter facilitates the selective frequency peaking of the passive network.

Abstract: A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.

Abstract: Coupled multi-inductors and their applications. An apparatus includes several circuit stages. Each circuit stage includes an inductive element that overlaps with the inductive elements of its adjacent circuit stages, forming a loop of coupled circuit stages. The apparatus may be, for example, a multi-phase oscillator with multiple oscillators that are magnetically coupled to each other for generating oscillation signals at different phases. The apparatus may also be, for example, a phase interpolator for combining input signals.

Abstract: An electronic device for wirelessly tracking the position of a second electronic device is disclosed. The electronic device includes transceiver circuitry having a beacon generator to generate a beacon at a particular frequency and direction. An antenna array transmits the beacon, and receives at least one reflected beacon from the second electronic device. The reflected beacon is received if a position of the second electronic device lies within a range of directions of the beacon. The transceiver circuitry further includes an injection-locked oscillator having an input coupled to the antenna array to receive reflected beacons, and to lock to the reflected beacon when the reflected beacon has a frequency value within locking range of the oscillator. Processing circuitry coupled to the transceiver circuitry tracks the position of the second device based on the lock condition of the oscillator.

Abstract: A transceiver includes a transmitter and receiver that form a series current path between two power-supply nodes. Powering both the transmitter and receiver with the same supply current saves power. The transmitter functions as a resistive load for the receiver, and thus performs useful work with power that would otherwise be dissipated as waste heat.

Abstract: A data buffer with a strobe-based primary interface and a strobe-less secondary interface used on a memory module is described. One memory module includes an address buffer, the data buffer and multiple dynamic random-access memory (DRAM) devices. The address buffer provides a timing reference to the data buffer and to the DRAM devices for one or more transactions between the data buffer and the DRAM devices via the strobe-less secondary interface.

Abstract: Embodiments of an integrated circuit (IC) comprising frequency change detection circuitry are described. Some embodiments include first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first clock frequency. The embodiments further include second circuitry to obtain samples by oversampling the first clock signal using the second clock signal. Additionally, the embodiments include third circuitry to detect a change in the first clock frequency based on the samples.

Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.

Abstract: A source-synchronous communication system in which a first integrated circuit (IC) conveys a data signal and concomitant strobe signal to a second IC. One or both ICs support hysteresis for the strobe channel that allows the second IC to distinguish between strobe preambles and noise, and thus prevent the false triggering of data capture. Hysteresis may also be employed to quickly settle the strobe channel to an inactive level after receipt of a strobe postamble.

Abstract: High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC.

Abstract: A linear equalizer (LEQ) includes a first transconductance device coupled to an input node of the LEQ and a second transconductance device AC coupled to the input node of the LEQ to increase a gain of the LEQ for data signals above a predetermined frequency. The first transconductance device and the second transconductance device are of complimentary types. A bimodal LEQ includes inputs to control operation of the bimodal LEQ in a current mode or a voltage mode. The bimodal LEQ includes first and second transconductance devices. One of the first and second transconductance devices is AC coupled to an input node to increase the gain for data signals above a predetermined frequency.

Abstract: A duty-cycle correction circuit calibrates the duty cycle of a periodic input signal. The correction circuit includes a state machine that samples the input signal using a sample signal of a sample period. The sample period is selected to scan a period of the input signal over a number of sample periods. The resultant difference between the number of high and low samples provides a measure of the duty cycle deviation from e.g. 50%. An adjustable delay circuit adjusts the relative timing of the rising and falling edges of the input signal, and thus the duty cycle, responsive to the measure of duty cycle.

Abstract: Encoder and decoder circuits that encode and decode a series of data words to/from a series of code words. The data words include L symbols. The code words include M symbols, where M is larger than L. A set of tightly coupled M links to convey respective symbols in each of the series of code words. The code words are selected such that between every two consecutive code words in a series of code words, an equal number of transitions from low to high and high to low occur on a subset of the M-links.

Abstract: A linear equalizer (LEQ) includes a first transconductance device coupled to an input node of the LEQ and a second transconductance device AC coupled to the input node of the LEQ to increase a gain of the LEQ for data signals above a predetermined frequency. The first transconductance device and the second transconductance device are of complimentary types. A bimodal LEQ includes inputs to control operation of the bimodal LEQ in a current mode or a voltage mode. The bimodal LEQ includes first and second transconductance devices. One of the first and second transconductance devices is AC coupled to an input node to increase the gain for data signals above a predetermined frequency.

Abstract: The disclosed embodiments relate to the design of a linear equalizer that supports low-power, high-speed data transfers. In some embodiments, this linear equalizer contains a passive network that provides selective frequency peaking in a frequency range associated with a falling edge of a frequency response of the channel. It also includes a level shifter coupled between the channel and the passive network, wherein the level shifter is an active component that provides amplification and/or level-shifting. Moreover, the linear equalizer is designed so that power from the level shifter facilitates the selective frequency peaking of the passive network.

Abstract: A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.

Abstract: High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC.

Abstract: A receiver includes an amplifier and a transconductance bias circuit. The amplifier gain is largely determined by transconductance and load impedance. The transconductance bias circuit varies the transconductance in inverse proportion to the load impedance to maintain the gain over process, voltage, and temperature. Differential amplifiers can use separate transconductance bias circuits for each amplifier leg, and the bias circuits can be independently controlled to minimize common-mode gain and voltage offsets.

Abstract: A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.

Abstract: A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.