Abstract: A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.

Abstract: A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.

Abstract: A circuit includes a clock generator to provide a clock signal, and a clock distribution circuit coupled to the clock generator and a plurality of pairs of outputs. The clock distribution circuit includes a plurality of adjustment circuits to generate a plurality of pairs of clock signals in accordance with the clock signal. A respective adjustment circuit in the plurality of adjustment circuits is to provide a respective pair of clock signals in the plurality of pairs of clock signals to a respective pair of outputs in the plurality of pairs of outputs. The respective pair of clock signals includes a first clock signal and a second clock signal. The first clock signal is a complement of the second clock signal and duty-cycle and skew errors in the first clock signal and the second clock signal are less than corresponding pre-determined values.

Abstract: A differential amplifier with adaptive biasing and offset cancellation is disclosed. In one particular exemplary embodiment, the differential amplifier may comprise a first electrical path comprising a first transistor and a first resistance element, and a second electrical path comprising a second transistor and a second resistance element, where the first and the second electrical paths are coupled to a voltage source on one end and to a current source on the other end. The differential amplifier may further comprise a first adjustable current source coupled between the voltage source and a first node located between the first transistor and the first resistance element, and a second adjustable current source coupled between the voltage source and a second node located between the second transistor and the second resistance element, wherein the first and second adjustable current sources provide biasing currents for the two electrical paths.

Abstract: A differential amplifier with adaptive biasing and offset cancellation is disclosed. In one particular exemplary embodiment, the differential amplifier may comprise a first electrical path comprising a first transistor and a first resistance element, and a second electrical path comprising a second transistor and a second resistance element, where the first and the second electrical paths are coupled to a voltage source on one end and to a current source on the other end. The differential amplifier may further comprise a first adjustable current source coupled between the voltage source and a first node located between the first transistor and the first resistance element, and a second adjustable current source coupled between the voltage source and a second node located between the second transistor and the second resistance element, wherein the first and second adjustable current sources provide biasing currents for the two electrical paths.