Patents by Inventor Katsuya Okumura
Katsuya Okumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9034467Abstract: According to one embodiment, a reticle chuck cleaner for cleaning a reticle chuck of an EUV exposure apparatus includes a substrate having a shape to be carried to the reticle chuck of the EUV exposure apparatus, and an adhesive formed on one of the main surfaces of the substrate.Type: GrantFiled: July 28, 2011Date of Patent: May 19, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masamitsu Itoh, Katsuya Okumura, Taro Inada, Jun Watanabe
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Patent number: 8859984Abstract: Provided is a method and an apparatus for inspecting a sample surface with high accuracy. Provided is a method for inspecting a sample surface by using an electron beam method sample surface inspection apparatus, in which an electron beam generated by an electron gun of the electron beam method sample surface inspection apparatus is irradiated onto the sample surface, and secondary electrons emanating from the sample surface are formed into an image toward an electron detection plane of a detector for inspecting the sample surface, the method characterized in that a condition for forming the secondary electrons into an image on a detection plane of the detector is controlled such that a potential in the sample surface varies in dependence on an amount of the electron beam irradiated onto the sample surface.Type: GrantFiled: July 30, 2013Date of Patent: October 14, 2014Assignee: Ebara CorporationInventors: Nobuharu Noji, Yoshihiko Naito, Hirosi Sobukawa, Kenji Terao, Masahiro Hatakeyama, Katsuya Okumura
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Publication number: 20130313429Abstract: Provided is a method and an apparatus for inspecting a sample surface with high accuracy. Provided is a method for inspecting a sample surface by using an electron beam method sample surface inspection apparatus, in which an electron beam generated by an electron gun of the electron beam method sample surface inspection apparatus is irradiated onto the sample surface, and secondary electrons emanating from the sample surface are formed into an image toward an electron detection plane of a detector for inspecting the sample surface, the method characterized in that a condition for forming the secondary electrons into an image on a detection plane of the detector is controlled such that a potential in the sample surface varies in dependence on an amount of the electron beam irradiated onto the sample surface.Type: ApplicationFiled: July 30, 2013Publication date: November 28, 2013Applicant: EBARA CORPORATIONInventors: Nobuharu Noji, Yoshihiko Naito, Hirosi Sobukawa, Kenji Terao, Masahiro Hatakeyama, Katsuya Okumura
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Patent number: 8531007Abstract: A semiconductor device is disclosed which includes active section 100, edge termination section 110 having a voltage blocking structure and disposed around active section 100, and separation section 120 having a device separation structure and disposed around edge termination section 110. A surface device structure is formed on the first major surface of active section 100, trench 23 is formed in separation section 120 from the second major surface side, and p+-type separation region 24 is formed on the side wall of trench 23 such that p+-type separation region 24 is in contact with p-type channel stopper region 21 formed in the surface portion on the first major surface side and p-type collector layer 9 formed in the surface portion on the second major surface side. The semiconductor device and the method for manufacturing the semiconductor device according to the invention facilitate preventing the reverse blocking voltage from decreasing and shorten the manufacturing time of the semiconductor device.Type: GrantFiled: May 20, 2010Date of Patent: September 10, 2013Assignees: Octec, Inc., Fuji Electric Co., Ltd.Inventors: Katsuya Okumura, Hiroki Wakimoto, Kazuo Shimoyama, Tomoyuki Yamazaki
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Patent number: 8525127Abstract: Provided is a method and an apparatus for inspecting a sample surface with high accuracy. Provided is a method for inspecting a sample surface by using an electron beam method sample surface inspection apparatus, in which an electron beam generated by an electron gun of the electron beam method sample surface inspection apparatus is irradiated onto the sample surface, and secondary electrons emanating from the sample surface are formed into an image toward an electron detection plane of a detector for inspecting the sample surface, the method characterized in that a condition for forming the secondary electrons into an image on a detection plane of the detector is controlled such that a potential in the sample surface varies in dependence on an amount of the electron beam irradiated onto the sample surface.Type: GrantFiled: February 16, 2012Date of Patent: September 3, 2013Assignee: Ebara CorporationInventors: Nobuharu Noji, Yoshihiko Naito, Hirosi Sobukawa, Kenji Terao, Masahiro Hatakeyama, Katsuya Okumura
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Patent number: 8416920Abstract: A target for X-ray generation has a substrate and a target portion. The substrate is comprised of diamond and has a first principal surface and a second principal surface opposed to each other. A bottomed hole is formed from the first principal surface side in the substrate. The target portion is comprised of a metal deposited from a bottom surface of the hole toward the first principal surface. An entire side surface of the target portion is in close contact with an inside surface of the hole.Type: GrantFiled: August 30, 2010Date of Patent: April 9, 2013Assignees: Tokyo Electron Limited, Hamamatsu Photonics K.K.Inventors: Katsuya Okumura, Katsuji Kadosawa, Tomofumi Kiyomoto, Motohiro Suyama, Atsushi Ishii
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Patent number: 8347744Abstract: Because a sample holder 100 is composed of a plurality of convex parts 1 provided on a top face of a base substance 2, and the plurality of convex parts 1 are spherical surfaces 1a formed of a single crystal or amorphous material, frictional wear of the sample at contact parts between a sample 4 and the convex parts 1 is reduced, thereby making it possible to inhibit particle generation. Further, because a joining layer 3 is formed of a single crystal or amorphous material, there is no defect that particles scattered on the sample holder 100 fill up it, which makes it possible to easily keep it in a clean state by cleaning, and it is possible to effectively reduce reattachment of particles to the sample 4.Type: GrantFiled: September 28, 2006Date of Patent: January 8, 2013Assignees: Kyocera Corporation, Okutec Co., Ltd.Inventors: Takeshi Muneishi, Toshihiko Uemura, Katsuya Okumura
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Patent number: 8324726Abstract: A semiconductor device that improves the heat cycle resistance and power cycle resistance of a power module. An electrode member in which copper posts are formed in a plurality of perforations cut in a support made of a ceramic material is soldered onto a side of an IGBT where an emitter electrode is formed. By soldering the copper posts onto the electrode, heat generated in the IGBT is transferred to the electrode member and is radiated. In addition, even if a material of which the IGBT is made and copper differ in thermal expansivity, stress on a soldered interface is reduced and distortion is reduced. This suppresses the appearance of a crack. As a result, the heat cycle resistance and power cycle resistance of a power module can be improved.Type: GrantFiled: February 10, 2006Date of Patent: December 4, 2012Assignees: Octec, Inc., Fuji Electric Co., Ltd., Kyocera CorporationInventors: Katsuya Okumura, Yoshikazu Takahashi, Kazunori Takenouchi
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Patent number: 8283755Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.Type: GrantFiled: May 13, 2011Date of Patent: October 9, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Nobuo Hayasaka, Katsuya Okumura, Keiichi Sasaki, Mie Matsuo
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Publication number: 20120244697Abstract: A semiconductor device that improves the heat cycle resistance and power cycle resistance of a power module. An electrode member in which copper posts are formed in a plurality of perforations cut in a support made of a ceramic material is soldered onto a side of an IGBT where an emitter electrode is formed. By soldering the copper posts onto the electrode, heat generated in the IGBT is transferred to the electrode member and is radiated. In addition, even if a material of which the IGBT is made and copper differ in thermal expansivity, stress on a soldered interface is reduced and distortion is reduced. This suppresses the appearance of a crack. As a result, the heat cycle resistance and power cycle resistance of a power module can be improved.Type: ApplicationFiled: June 11, 2012Publication date: September 27, 2012Applicants: Octec, Inc., Kyocera Corporation, Fuji Electric Device Technology Co., Ltd.Inventors: Katsuya Okumura, Yoshikazu Takahashi, Kazunori Takenouchi
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Patent number: 8247289Abstract: A capacitor having a high quality and a manufacturing method of the same are provided. A capacitor has a lower electrode formed on an oxide film, a dielectric layer formed on the lower electrode, an upper electrode formed so as to face the lower electrode with the dielectric layer between, and an upper electrode formed so as to cover the upper electrode, an opening portion of the upper electrode and an opening portion of the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to pattern the dielectric layer by using the upper electrode as a mask, and provide a capacitor having a high-quality dielectric layer by preventing impurity diffusion into the dielectric layer. By forming the upper electrode on the dielectric layer, it is possible to prevent the dielectric layer from being exposed to etching liquid, liquid developer, etc.Type: GrantFiled: August 23, 2006Date of Patent: August 21, 2012Assignee: Ibiden Co., Ltd.Inventors: Yoshiki Yamanishi, Muneo Harada, Takahiro Kitano, Tatsuzo Kawaguchi, Yoshihiro Hirota, Kinji Yamada, Tomotaka Shinoda, Katsuya Okumura, Shuichi Kawano
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Publication number: 20120145921Abstract: Provided is a method and an apparatus for inspecting a sample surface with high accuracy. Provided is a method for inspecting a sample surface by using an electron beam method sample surface inspection apparatus, in which an electron beam generated by an electron gun of the electron beam method sample surface inspection apparatus is irradiated onto the sample surface, and secondary electrons emanating from the sample surface are formed into an image toward an electron detection plane of a detector for inspecting the sample surface, the method characterized in that a condition for forming the secondary electrons into an image on a detection plane of the detector is controlled such that a potential in the sample surface varies in dependence on an amount of the electron beam irradiated onto the sample surface.Type: ApplicationFiled: February 16, 2012Publication date: June 14, 2012Applicant: EBARA CORPORATIONInventors: Nobuharu Noji, Yoshihiko Naito, Hirosi Sobukawa, Kenji Terao, Masahiro Hatakeyama, Katsuya Okumura
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Patent number: 8174093Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.Type: GrantFiled: October 26, 2010Date of Patent: May 8, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Nobuo Hayasaka, Katsuya Okumura, Keiichi Sasaki, Mie Matsuo
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Publication number: 20120024318Abstract: According to one embodiment, a reticle chuck cleaner for cleaning a reticle chuck of an EUV exposure apparatus includes a substrate having a shape to be carried to the reticle chuck of the EUV exposure apparatus, and an adhesive formed on one of the main surfaces of the substrate.Type: ApplicationFiled: July 28, 2011Publication date: February 2, 2012Inventors: Masamitsu ITOH, Katsuya Okumura, Taro Inada, Jun Watanabe
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Patent number: 8071157Abstract: There is disclosed a film forming method comprising continuously discharging a solution adjusted so as to spread over a substrate by a given amount to the substrate through a discharge port disposed in a nozzle, moving the nozzle and substrate with respect to each other, and holding the supplied solution onto the substrate to form a liquid film, wherein a distance h between the discharge port of the nozzle and the substrate is set to be not less than 2 mm and to be in a range less than 5×10?5 q? (mm) given with respect to a surface tension ? (N/m) of the solution, discharge speed q (m/sec) of the solution continuously discharged through the discharge port, and a constant of 5×10?5 (m·sec/N).Type: GrantFiled: December 3, 2007Date of Patent: December 6, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Shinichi Ito, Tatsuhiko Ema, Kei Hayasaki, Rempei Nakata, Nobuhide Yamada, Katsuya Okumura
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Patent number: 8021062Abstract: A developing apparatus has a substrate holder to hold a substrate, a heater which is provided in a substrate holder, and heats a substrate on a substrate holder for processing a resist film by PEB, a cooler to cool a substrate on a substrate holder, a developing solution nozzle to supply a developing solution to a substrate on a substrate holder, and a controller to control a heater, a cooler and a developing nozzle.Type: GrantFiled: May 5, 2010Date of Patent: September 20, 2011Assignees: Tokyo Electron Limited, Octec Inc.Inventors: Takanori Nishi, Takahiro Kitano, Katsuya Okumura
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Publication number: 20110215443Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.Type: ApplicationFiled: May 13, 2011Publication date: September 8, 2011Inventors: Nobuo Hayasaka, Katsuya Okumura, Keiichi Sasaki, Mie Matsuo
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Publication number: 20110212255Abstract: There is disclosed a film forming method comprising continuously discharging a solution adjusted so as to spread over a substrate by a given amount to the substrate through a discharge port disposed in a nozzle, moving the nozzle and substrate with respect to each other, and holding the supplied solution onto the substrate to form a liquid film, wherein a distance h between the discharge port of the nozzle and the substrate is set to be not less than 2 mm and to be in a range less than 5×10?5 q? (mm) given with respect to a surface tension ? (N/m) of the solution, discharge speed q (m/sec) of the solution continuously discharged through the discharge port, and a constant of 5×10?5 (m·sec/N).Type: ApplicationFiled: December 3, 2007Publication date: September 1, 2011Inventors: Shinichi Ito, Tatsuhiko Ema, Kei Hayasaki, Rempei Nakata, Nobuhide Yamada, Katsuya Okumura
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Patent number: 7994443Abstract: A first wiring layer 16 is disposed on an insulating film 14 on the lower surface of an upper substrate 15, while a second wiring layer 13three-dimensionally crossing the first wiring layer 16 is provided on the insulating film 12 on a lower substrate 11. A cantilever 17 has one end connected to the first wiring layer 16 and the other end opposed to the second wiring layer 13 with a space therebetween. A thermoplastic sheet 19 is arranged on the upper substrate 15 so as to cover the through-hole 18. The thermoplastic sheet 19 is pressed by a heated pin 20 against the cantilever 17 and deformed so as to maintain the connection between the cantilever 17and the second wiring layer 13, and therefore close the switch 10.Type: GrantFiled: March 20, 2006Date of Patent: August 9, 2011Assignees: Tokyo Electron Limited, Octec Inc.Inventors: Masato Hayashi, Masami Yakabe, Tetsuya Hasebe, Muneo Harada, Katsuya Okumura
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Patent number: 7988429Abstract: A chemical liquid supply system that prevents the generation of heat during operation in a pump and allows downsizing the discharge pump for instilling a chemical liquid from a tip nozzle. Compressed air is supplied to an upper space of a resist bottle and the chemical liquid is conferred positive pressure and sent out to a pump chamber of a discharge pump, thereby the pump chamber is filled with a resist liquid. This eliminates the need of a conventional construction where a spring or others are used to drive a flexible membrane of the discharge pump to the operation chamber side to take in the resist liquid. As a result, no electric motor is used, so there is obviously no risk of heat damage to a semiconductor wafer and the discharge pump itself can be further downsized.Type: GrantFiled: July 29, 2005Date of Patent: August 2, 2011Assignees: Octec Inc., Tokyo Electron LimitedInventors: Katsuya Okumura, Shigenobu Itoh, Tetsuya Toyoda, Kazuhiro Sugata