Abstract: A semiconductor device and a stacked pillar used to interconnect a first semiconductor die and a second semiconductor die are provided. The semiconductor device has a substrate, a splice interposer, a first semiconductor die, a second semiconductor die and first to fourth plurality of pillars. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate. The stacked pillar has a first conductor layer formed on a surface of the first semiconductor die, a first solder layer formed on the first conductor layer, a second conductor layer formed on the first solder layer, and a second solder layer formed on the second conductor layer. The second solder layer is heat-reflowable to attach the stacked pillar to a surface of the second semiconductor.

Abstract: A method includes measuring, using at least one sensor, strain on a nail plate of a subject, wherein the at least one sensor outputs a data stream corresponding to the measuring, communicating the data stream to a receiver, and interpreting, by the receiver, the data stream to determine a parameter of interest of the subject.

Abstract: An apparatus for monitoring strain caused by bodily fluids or tissues in contact with an implantable medical device includes at least one strain gauge sensor embedded within the implantable medical device. The strain gauge sensor is configured to measure a mechanical strain of the implantable medical device. The apparatus further includes a processor module coupled with the strain gauge sensor. The processor module is configured to receive a sense signal generated by the strain gauge sensor and to extract therefrom a measurement of strain caused by bodily fluids or tissues in contact with the implantable medical device.

Abstract: A sensor includes a bridge circuit including one or more strain gauges mounted on a nail plate, the bridge circuit outputting a voltage signal, an amplifier circuit amplifying the voltage signal output by the bridge circuit to generate an amplified signal, an analog-to-digital (A/D) converter converting the amplified signal into a digital signal, a controller receiving the digital signal and facilitating communication with a receiver, and an antenna configured to transmit the digital signal.

Abstract: A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.

Abstract: Aspects include a method of manufacturing a flexible electronic structure that includes a metal or doped silicon substrate. Aspects include depositing an insulating layer on a silicon substrate. Aspects also include patterning a metal on a silicon substrate. Aspects also include selectively masking the structure to expose the metal and a portion of the silicon substrate. Aspects also include depositing a conductive layer including a conductive metal on the structure. Aspects also include plating the conductive material on the structure. Aspects also include spalling the structure.

Abstract: A fluxless bonding process is provided. An array of micro solder bumps of a first semiconductor structure is aligned to an array of bonding pads of a second semiconductor structure under an applied bonding force. An environment is provided to prevent oxides from forming on the solder bump structures and bonding pads during the bonding process. A scrubbing process is performed at a given scrubbing frequency and amplitude to scrub the micro solder bumps against the bonding pads in a direction perpendicular to the bonding. Heat is applied to at least the first semiconductor structure to melt and bond the micro solder bumps to the bonding pads. The first semiconductor structure is cooled down to solidify the molten solder. Coplanarity is maintained between the bonding surfaces of the semiconductor structures within a given tolerance during the scrubbing and cooling steps until solidification of the micro solder bumps.

Abstract: A method and apparatus for flip chip bonding using conductive and inductive heating to heat a plurality of solder bumps located between a chip carrier and a chip.

Abstract: A method of forming a 3D package. The method may include joining an interposer to a laminate chip carrier with the solid state diffusion of a first plurality of solder bumps by applying a first selective non-uniform heat and first uniform pressure; joining a top chip to the interposer with the solid state diffusion of a second plurality of solder bumps by applying a second selective non-uniform heat and second uniform pressure; heating the 3D package, the first and second pluralities of solder bumps to a temperature greater than the reflow temperature of the first and second pluralities of solder bumps, where the second plurality of solder bumps achieves the reflow temperature before the first plurality of solder bumps, where the first and second selective non-uniform heats being less that the reflow temperature of the first and second pluralities of solder bumps, respectively.

Abstract: Arrays of objects on a substrate having void-free underfill as well as methods and systems of forming the same include forming a void-free layer of underfill material between a substrate and an array of multiple objects positioned on the substrate. The void-free layer of underfill material is cured to form a protective cured underfill layer that provides structural support to connections between the objects and the substrate.

Abstract: Alignment marks on a semiconductor device surface are exposed and exposed surfaces cleaned after an obscuring coating is applied over the surface and marks. The surface can be an attachment surface of the device and can include C4 solder bumps of a flip-chip type device and the coating can include a wafer level underfill coating that is substantially optically opaque. Laser ablation, such as with a UV laser, can remove the coating while minimizing heat transfer to the device.

Abstract: Aspects include a method of manufacturing a flexible electronic structure that includes a metal or doped silicon substrate. Aspects include depositing an adhesive layer on the top side of the structure. Aspects also include depositing a release layer and a glass layer on the top side of the structure. Aspects also include reducing a thickness of the silicon substrate on the bottom side of the structure.

Abstract: Arrays of objects on a substrate having void-free underfill as well as methods and systems of forming the same include forming a void-free layer of underfill material between a substrate and an array of multiple objects positioned on the substrate. The void-free layer of underfill material is cured to form a protective cured underfill layer that provides structural support to connections between the objects and the substrate.

Abstract: Arrays of objects on a substrate having void-free underfill as well as methods and systems of forming the same include forming a void-free layer of underfill material between a substrate and an array of multiple objects positioned on the substrate. The void-free layer of underfill material is cured to form a protective cured underfill layer that provides structural support to connections between the objects and the substrate.

Abstract: A method of forming a reduced volume interconnect for a chip stack including multiple silicon layers, the method including: forming multiple conductive structures, each of at least a subset of the conductive structures having a volume of conductive material for a corresponding under bump metallurgy pad onto which the conductive structure is transferred that is configured such that a ratio of an unreflowed diameter of the conductive structure to a diameter of the corresponding pad is about one third-to-one or less; transferring the conductive structures to the silicon layers; stacking the silicon layers in a substantially vertical dimension such that each of the conductive structures on a given silicon layer is aligned with a corresponding electrical contact location on an underside of an adjacent silicon layer; and heating the interconnect so as to metallurgically bond multiple electrical contact locations of adjacent silicon layers.

Abstract: Aspects include a method of manufacturing a flexible electronic structure that includes a metal or doped silicon substrate. Aspects include depositing an insulating layer on a silicon substrate. Aspects also include patterning a metal on a silicon substrate. Aspects also include selectively masking the structure to expose the metal and a portion of the silicon substrate. Aspects also include depositing a conductive layer including a conductive metal on the structure. Aspects also include plating the conductive material on the structure. Aspects also include spalling the structure.

Abstract: An interposer structure and a method of interconnecting first and second semiconductor dies are provided. A splice interposer is attached to a top surface of a substrate through a first plurality of pillars formed on a bottom surface of the splice interposer. The first semiconductor die is attached to the top surface of a substrate through a second plurality of pillars formed on a bottom surface of the first semiconductor die. The first semiconductor die is attached to a top surface of the splice interposer through a third plurality of pillars formed on the bottom surface of the first semiconductor. The height of the second plurality of pillars is greater than the height of the third plurality of pillars. The second semiconductor die is attached to the top surface of the splice interposer through a fourth plurality of pillars formed on a bottom surface of the second semiconductor die.

Abstract: Structures and methods for improving the visualization of alignment marks on an underfill-covered chip. A feature is formed on a chip, and an underfill material is applied to the chip at a wafer level so that the feature is covered the feature. The feature includes a first structural element comprised of a first material and a second structural element comprised of a second material that is electrochemically dissimilar from the first material to provide a galvanic cell effect. Filler particles in the underfill material are caused by the galvanic cell effect to distribute with a first density in a first region over the first structural element and a second region of a second density over the second structural element. The first density in the first region is less than the second density in the second region such that the first region has a lower opacity than the second region.

Abstract: A fluxless bonding process is provided. An array of micro solder bumps of a first semiconductor structure is aligned to an array of bonding pads of a second semiconductor structure under an applied bonding force. An environment is provided to prevent oxides from forming on the solder bump structures and bonding pads during the bonding process. A scrubbing process is performed at a given scrubbing frequency and amplitude to scrub the micro solder bumps against the bonding pads in a direction perpendicular to the bonding. Heat is applied to at least the first semiconductor structure to melt and bond the micro solder bumps to the bonding pads. The first semiconductor structure is cooled down to solidify the molten solder. Coplanarity is maintained between the bonding surfaces of the semiconductor structures within a given tolerance during the scrubbing and cooling steps until solidification of the micro solder bumps.

Abstract: A method of interconnecting first and second semiconductor dies is provided. A splice interposer is attached to a top surface of a substrate through first pillars formed on a bottom surface of the splice interposer. The first semiconductor die is attached to the top surface of a substrate through second pillars formed on a bottom surface of the first semiconductor die. The first semiconductor die is attached to a top surface of the splice interposer through third pillars formed on the bottom surface of the first semiconductor. The second semiconductor die is attached to the top surface of the splice interposer through fourth pillars formed on a bottom surface of the second semiconductor die. The first to fourth plurality of pillars and the splice interposer form interconnection and wiring between the first semiconductor die, the second semiconductor die and the substrate.