Patents by Inventor Kazuhiro Kurihara
Kazuhiro Kurihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11970834Abstract: The invention includes a vehicle main body, a boom, a first actuator connecting the boom and the vehicle main body and configured to rotate the boom with respect to the vehicle main body about a first central axis, a first electric motor connected to the first actuator and that operates the first actuator. The boom includes a pair of boom lateral plates disposed to face each other in a direction of the first central axis, and a boom bottom plate connecting the boom lateral plates to each other, the first electric motor being disposed in a boom internal space surrounded by the pair of boom lateral plates and the boom bottom plate.Type: GrantFiled: June 12, 2020Date of Patent: April 30, 2024Assignee: Komatsu Ltd.Inventors: Ryo Ishikawa, Kazuhiro Kurihara, Takeshi Endou
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Publication number: 20230351063Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for signal encryption in high bandwidth memory. A high bandwidth memory (HBM) may include a mix of secure circuits and non-secure circuits, which are coupled to secure and non-secure registers respectively. Information may be communicated between the secure and non-secure registers along an interface. The information associated with the secure register may be encrypted. When information is written to the secure register, an encryption circuit in the HBM may first decrypt the information before it is written to the secure register. When information is read from the secure register, it may first be encrypted by the encryption circuit before it is provided along the interface.Type: ApplicationFiled: June 12, 2023Publication date: November 2, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Chikara Kondo, Kazuhiro Kurihara
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Patent number: 11720719Abstract: Apparatuses, systems, and methods for signal encryption in high bandwidth memory are described. A high bandwidth memory (HBM) may include a mix of secure circuits and non-secure circuits, which are coupled to secure and non-secure registers respectively. Information may be communicated between the secure and non-secure registers along an interface. The information associated with the secure register may be encrypted. When information is written to the secure register, an encryption circuit in the HBM may first decrypt the information before it is written to the secure register. When information is read from the secure register, it may first be encrypted by the encryption circuit before it is provided along the interface.Type: GrantFiled: October 1, 2019Date of Patent: August 8, 2023Assignee: Micron Technology, Inc.Inventors: Chikara Kondo, Kazuhiro Kurihara
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Publication number: 20210381193Abstract: The invention includes a vehicle main body, a boom, a first actuator connecting the boom and the vehicle main body and configured to rotate the boom with respect to the vehicle main body about a first central axis, a first electric motor connected to the first actuator and that operates the first actuator. The boom includes a pair of boom lateral plates disposed to face each other in a direction of the first central axis, and a boom bottom plate connecting the boom lateral plates to each other, the first electric motor being disposed in a boom internal space surrounded by the pair of boom lateral plates and the boom bottom plate.Type: ApplicationFiled: June 12, 2020Publication date: December 9, 2021Applicant: Komatsu Ltd.Inventors: Ryo Ishikawa, Kazuhiro Kurihara, Takeshi Endou
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Publication number: 20210097209Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for signal encryption in high bandwidth memory. A high bandwidth memory (HBM) may include a mix of secure circuits and non-secure circuits, which are coupled to secure and non-secure registers respectively. Information may be communicated between the secure and non-secure registers along an interface. The information associated with the secure register may be encrypted. When information is written to the secure register, an encryption circuit in the HBM may first decrypt the information before it is written to the secure register. When information is read from the secure register, it may first be encrypted by the encryption circuit before it is provided along the interface.Type: ApplicationFiled: October 1, 2019Publication date: April 1, 2021Applicant: MICRON TECHNOLOGY, INC.Inventors: Chikara Kondo, Kazuhiro Kurihara
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Patent number: 10803923Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.Type: GrantFiled: June 18, 2019Date of Patent: October 13, 2020Assignee: Micron Technology, Inc.Inventors: Katsuhiro Kitagawa, Kazuhiro Kurihara, Kohei Nakamura, Akira Yamashita
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Publication number: 20190304532Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.Type: ApplicationFiled: June 18, 2019Publication date: October 3, 2019Applicant: Micron Technology, Inc.Inventors: Katsuhiro Kitagawa, Kazuhiro Kurihara, Kohei Nakamura, Akira Yamashita
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Patent number: 10339998Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.Type: GrantFiled: March 27, 2018Date of Patent: July 2, 2019Assignee: Micron Technology, Inc.Inventors: Katsuhiro Kitagawa, Kazuhiro Kurihara, Kohei Nakamura, Akira Yamashita
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Patent number: 9162858Abstract: To facilitate loading-unloading operation of a battery even when a large-sized battery is mounted, in a battery-powered forklift which is driven with power of a battery mounted on a vehicle body including a fork which is arranged at a front part of the vehicle body, a counter weight which is arranged at a rear part of the vehicle body, and a top plate which is supported at a position to cover an area above a driver seat via a pair of rear stays 44 extended upward from both sides of the rear part of the vehicle body, post members arranged in a raised manner at both sides of the counter weight guide movement of the battery along the front-rear direction of the vehicle body between the post members.Type: GrantFiled: March 13, 2012Date of Patent: October 20, 2015Assignee: Komatsu Ltd.Inventors: Kouji Nishiyama, Kazuhiro Kurihara
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Patent number: 8933849Abstract: A slide type portable wireless device includes: a first housing; a second housing which slides relative to the first housing, and is positioned at either of a first relative position and a second relative position different from the first relative position; an antenna element which is embedded in the first housing; and a plurality of parasitic elements which are provided in the second housing, and includes first and second parasitic elements capacity coupled with the antenna element. The first parasitic element faces the antenna element at the first relative position. The second parasitic element faces the antenna element at the second relative position.Type: GrantFiled: March 28, 2011Date of Patent: January 13, 2015Assignee: Lenovo Innovations Limited (Hong Kong)Inventor: Kazuhiro Kurihara
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Publication number: 20140238780Abstract: A battery type forklift which is driven with power of a battery mounted on a vehicle body, includes: a fork arranged at a front part of the vehicle body; and a counter weight arranged at a rear part of the vehicle body, wherein the battery is mounted on the vehicle body in a state of being capable of being removed to a rear side of the vehicle body, and the counter weight comprises a guide unit which prevents sway of the battery in a right-left direction of the vehicle body when removing the battery and which guides movement of the battery along a front-rear direction of the vehicle body.Type: ApplicationFiled: March 13, 2012Publication date: August 28, 2014Applicant: KOMATSU LTD.Inventors: Kouji Nishiyama, Kazuhiro Kurihara
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Patent number: 8789636Abstract: A battery-powered forklift including a fork placed at an anterior portion of a vehicle body, and a counter weight placed at a posterior portion of the vehicle body, the battery-powered forklift running by electric power of a battery mounted on the vehicle body, wherein a concave portion that is open in a longitudinal direction is formed at an upper surface of the counter weight, the battery is mounted on a position above a rear wheel of the vehicle body while at least a part of the battery overlaps with the counter weight, and the battery is removable toward a rear of the vehicle body through the concave portion of the counter weight.Type: GrantFiled: March 13, 2012Date of Patent: July 29, 2014Assignee: Komatsu Ltd.Inventors: Kouji Nishiyama, Kazuhiro Kurihara, Tetsuya Okuyama
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Patent number: 8699283Abstract: The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.Type: GrantFiled: February 19, 2013Date of Patent: April 15, 2014Assignee: Spansion LLCInventors: Hiroaki Wada, Kazuhiro Kurihara
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Publication number: 20140020967Abstract: A battery-powered forklift including a fork placed at an anterior portion of a vehicle body, and a counter weight placed at a posterior portion of the vehicle body, the battery-powered forklift running by electric power of a battery mounted on the vehicle body, wherein a concave portion that is open in a longitudinal direction is formed at an upper surface of the counter weight, the battery is mounted on a position above a rear wheel of the vehicle body while at least a part of the battery overlaps with the counter weight, and the battery is removable toward a rear of the vehicle body through the concave portion of the counter weight.Type: ApplicationFiled: March 13, 2012Publication date: January 23, 2014Applicant: KOMATSU LTD.Inventors: Kouji Nishiyama, Kazuhiro Kurihara, Tetsuya Okuyama
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Patent number: 8379472Abstract: The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.Type: GrantFiled: June 7, 2011Date of Patent: February 19, 2013Assignee: Spansion LLCInventors: Hiroaki Wada, Kazuhiro Kurihara
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Publication number: 20130009829Abstract: A slide type portable wireless device includes: a first housing; a second housing which slides relative to the first housing, and is positioned at either of a first relative position and a second relative position different from the first relative position; an antenna element which is embedded in the first housing; and a plurality of parasitic elements which are provided in the second housing, and includes first and second parasitic elements capacity coupled with the antenna element. The first parasitic element faces the antenna element at the first relative position. The second parasitic element faces the antenna element at the second relative position.Type: ApplicationFiled: March 28, 2011Publication date: January 10, 2013Applicant: NEC CORPORATIONInventor: Kazuhiro Kurihara
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Publication number: 20110234856Abstract: The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.Type: ApplicationFiled: June 7, 2011Publication date: September 29, 2011Inventors: Hiroaki WADA, Kazuhiro KURIHARA
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Patent number: 7957205Abstract: The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.Type: GrantFiled: October 6, 2009Date of Patent: June 7, 2011Assignee: Spansion LLCInventors: Hiroaki Wada, Kazuhiro Kurihara
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Patent number: 7903473Abstract: A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among sectors during erasing the data in the first sector, said pair of sectors being the first sector and the second sector; and an SRAM array (storage) (30) retaining the data of the second sector. The present invention can provide a semiconductor device in which a reduced number of sector select circuits is used so that the area of memory cell array can be reduced and provide a method of controlling the semiconductor device.Type: GrantFiled: July 23, 2009Date of Patent: March 8, 2011Assignee: Spansion LLCInventors: Hiroki Murakami, Kazuhiro Kurihara
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Patent number: D731736Type: GrantFiled: July 8, 2013Date of Patent: June 9, 2015Assignee: KOMATSU LTD.Inventors: Kazuhiro Kurihara, Norikazu Nakazawa, Kazuhiro Kurita, Teruhisa Iwata, Kouhei Miyazaki