Abstract: A semiconductor device includes a first memory cell array that includes memory cells for storing data and is managed on a sector basis, a second memory cell array including memory cells storing sector protection information on the sector basis, and a control circuit checking the sector protection information stored in the second memory cell array whenever the sector to be programmed or erased is selected. Thus, the sector protection information in all the sectors does not have to be latched at the time of power on. The latch circuit equal in number to the sector does not have to be provided. It is thus possible to reduce the number of the circuits drastically and the chip area can be reduced.

Abstract: The semiconductor device of the present invention includes a column decoder (select and write circuit), which selects multiple pages that are not located adjacently to each other so as to simultaneously program multiple bits in the memory cells of the selected page, when the multiple bits are programmed in the multiple pages. The page is a selection unit and is composed of a given number of the memory cells located on a same word line. An unnecessary stress of programming is not applied to the memory cells that are not to be programmed, by increasing the distance between the memory cells to be programmed simultaneously.

Abstract: The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.

Abstract: A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among sectors during erasing the data in the first sector, said pair of sectors being the first sector and the second sector; and an SRAM array (storage) (30) retaining the data of the second sector. The present invention can provide a semiconductor device in which a reduced number of sector select circuits is used so that the area of memory cell array can be reduced and provide a method of controlling the semiconductor device.

Abstract: A nonvolatile semiconductor memory device is disclosed that comprises plural sectors each including a memory cell array, plural word line drivers provided in each one of the sectors to drive respective word lines, and sector switches provided one for each sector. The sector switches are connected to the plural word line drivers in the corresponding sector, adapted to provide a negative voltage to be applied to the word lines to the plural word line drivers when the corresponding sector is selected for an erase operation. The sector switches only include transistors directly connected to an output signal line to provide the negative voltage to the word line drivers. A decoding circuit shared by one or more sectors is adapted to control the sector switches to allow a sector switch in a selected sector to output the negative voltage and allow a sector switch in an unselected sector to output a voltage different from the negative voltage.

Abstract: The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.

Abstract: A non-volatile semiconductor memory includes a first pump starting to operate at a first timing and producing a first voltage, a second pump starting to operate at a second timing following the first timing and driving a given node at a second voltage, the given node being connected to a non-volatile semiconductor memory cell, and a booster boosting the given node using the first voltage at the second timing.

Abstract: A transmission circuit includes a baseband circuit, spreading section, multiplier, digital modulator, quadrature modulator, and antenna. The baseband circuit generates and outputs at least one transmission data constituted by first and second channel data. The spreading section spreads the transmission data with a spreading code that differs for each transmission channel. The multiplier respectively weights the amplitudes of the first and second channel data by using a combination of two gain factors determined by a transmission data rate. The digital modulator digitally modulates the first and second channel data whose amplitudes are weighted by the multiplier. The quadrature modulator quadrature-modulates the digitally modulated first and second channel data and outputs the data as a transmission signal. The antenna emits the transmission signal output from the quadrature modulator as a radio wave.

Abstract: A semiconductor device includes a first memory cell array that includes memory cells for storing data and is managed on a sector basis, a second memory cell array including memory cells storing sector protection information on the sector basis, and a control circuit checking the sector protection information stored in the second memory cell array whenever the sector to be programmed or erased is selected. Thus, the sector protection information in all the sectors does not have to be latched at the time of power on. The latch circuit equal in number to the sector does not have to be provided. It is thus possible to reduce the number of the circuits drastically and the chip area can be reduced.

Abstract: The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.

Abstract: A nonvolatile semiconductor memory device includes nonvolatile memory cells each configured to store 2-bit information per memory cell, and a control circuit configured to verify with a first threshold one or more bits subjected to writing of new data and to verify with a second threshold one or more bits subjected to refreshing of existing data in a program operation that performs the writing of new data and the refreshing of existing data simultaneously with respect to the nonvolatile memory cells, the second threshold being lower than the first threshold.

Abstract: A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected. Each of the sectors includes a pull-up transistor that is driven by a corresponding one of the decoders via a corresponding one of global word lines connecting the sectors and drives one of the local word lines, and the pull-up transistor is kept OFF by the control signal.

Abstract: A non-volatile semiconductor memory includes a first pump starting to operate at a first timing and producing a first voltage, a second pump starting to operate at a second timing following the first timing and driving a given node at a second voltage, the given node being connected to a non-volatile semiconductor memory cell, and a booster boosting the given node using the first voltage at the second timing.

Abstract: The semiconductor device of the present invention includes a column decoder (select and write circuit), which selects multiple pages that are not located adjacently to each other so as to simultaneously program multiple bits in the memory cells of the selected page, when the multiple bits are programmed in the multiple pages. The page is a selection unit and is composed of a given number of the memory cells located on a same word line. An unnecessary stress of programming is not applied to the memory cells that are not to be programmed, by increasing the distance between the memory cells to be programmed simultaneously.

Abstract: The semiconductor device includes a memory cell array that includes memory cells for storing data and is managed on a sector basis, a memory that stores the information determining the activation status, a latch circuit that latches the activation information according to the information stored in the memory, and a circuit that latches the activation information according to the information stored in the memory in the latch circuit. The activation information according to the memory state of the memory is latched at the time of inputting a given command after activation, and it is thus possible to read the information stored in the memory and set the information in the latch circuit certainly.

Abstract: A method for controlling gate voltage in a memory device is described. The method includes providing a circuit that is adapted to be coupled with the memory device. The circuit is for generating a reference voltage. The method further includes utilizing the reference voltage provided by the circuit to apply a voltage at a gate of the memory device. The voltage has a value corresponding to a temperature of the memory device. The method also includes retaining a proportional relationship between the reference voltage and the temperature of the memory device, regardless of the change in the temperature of the memory device. The reference voltage provides a substantially constant programming time for the memory device regardless of the temperature of the memory device.

Abstract: When a received character data is decoded by a decoder 10, a word division circuit 21 divides the data into word units, and a voice storage circuit 22 outputs a voice data corresponding to the divided character data, and a D/A converter 30 converts it into an analog signal, and it is output from a speaker 40 as voice. Thereby, the character data is output as voice. An output from the decoder 10 is stored in a memory 50, and is displayed on an LCD 60 as a character. The LCD 60 receives a byte number of a word for every word from the word division circuit 21, and highlights it for every byte number.

Abstract: A nonvolatile semiconductor memory device includes nonvolatile memory cells each configured to store 2-bit information per memory cell, and a control circuit configured to verify with a first threshold one or more bits subjected to writing of new data and to verify with a second threshold one or more bits subjected to refreshing of existing data in a program operation that performs the writing of new data and the refreshing of existing data simultaneously with respect to the nonvolatile memory cells, the second threshold being lower than the first threshold.

Abstract: A nonvolatile semiconductor memory device is disclosed that comprises plural sectors each including a memory cell array, plural word line drivers provided in each one of the sectors to drive respective word lines, and sector switches provided one for each sector. The sector switches are connected to the plural word line drivers in the corresponding sector, adapted to provide a negative voltage to be applied to the word lines to the plural word line drivers when the corresponding sector is selected for an erase operation. The sector switches only include transistors directly connected to an output signal line to provide the negative voltage to the word line drivers. A decoding circuit shared by one or more sectors is adapted to control the sector switches to allow a sector switch in a selected sector to output the negative voltage and allow a sector switch in an unselected sector to output a voltage different from the negative voltage.

Abstract: A variable type antenna matching circuit includes an antenna, shape change detecting section, transmission/reception radio section, and variable type antenna matching section. The shape change detecting section detects a change in the shape of the housing of a portable terminal. The transmission/reception radio section transmits and receives signals. The variable type antenna matching section changes the input impedance between the antenna and the transmission/reception radio section in accordance with an output signal from the shape change detecting section.