Patents by Inventor Kazuhiro Kurihara
Kazuhiro Kurihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7903473Abstract: A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among sectors during erasing the data in the first sector, said pair of sectors being the first sector and the second sector; and an SRAM array (storage) (30) retaining the data of the second sector. The present invention can provide a semiconductor device in which a reduced number of sector select circuits is used so that the area of memory cell array can be reduced and provide a method of controlling the semiconductor device.Type: GrantFiled: July 23, 2009Date of Patent: March 8, 2011Assignee: Spansion LLCInventors: Hiroki Murakami, Kazuhiro Kurihara
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Patent number: 7898879Abstract: The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.Type: GrantFiled: October 6, 2009Date of Patent: March 1, 2011Assignee: Spansion LLCInventors: Hiroaki Wada, Kazuhiro Kurihara
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Patent number: 7889577Abstract: A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among sectors during erasing the data in the first sector, said pair of sectors being the first sector and the second sector; and an SRAM array (storage) (30) retaining the data of the second sector. The present invention can provide a semiconductor device in which a reduced number of sector select circuits is used so that the area of memory cell array can be reduced and provide a method of controlling the semiconductor device.Type: GrantFiled: June 25, 2009Date of Patent: February 15, 2011Assignee: Spansion LLCInventors: Hiroki Murakami, Kazuhiro Kurihara
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Patent number: 7821833Abstract: A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected. Each of the sectors includes a pull-up transistor that is driven by a corresponding one of the decoders via a corresponding one of global word lines connecting the sectors and drives one of the local word lines, and the pull-up transistor is kept OFF by the control signal.Type: GrantFiled: September 15, 2008Date of Patent: October 26, 2010Assignee: Spansion LLCInventors: Yasuhiko Tanuma, Kazuhiro Kurihara
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Patent number: 7729170Abstract: A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected. Each of the sectors includes a pull-up transistor that is driven by a corresponding one of the decoders via a corresponding one of global word lines connecting the sectors and drives one of the local word lines, and the pull-up transistor is kept OFF by the control signal.Type: GrantFiled: September 15, 2008Date of Patent: June 1, 2010Assignee: Spansion LLCInventors: Yasuhiko Tanuma, Kazuhiro Kurihara
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Publication number: 20100020214Abstract: The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.Type: ApplicationFiled: October 6, 2009Publication date: January 28, 2010Inventors: Hiroaki WADA, Kazuhiro KURIHARA
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Publication number: 20100020598Abstract: The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.Type: ApplicationFiled: October 6, 2009Publication date: January 28, 2010Inventors: Hiroaki WADA, Kazuhiro KURIHARA
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Patent number: 7643371Abstract: A semiconductor device and a method of controlling the semiconductor device, the semiconductor device including: a memory cell array; a terminal that inputs or outputs storage data stored in the memory cell array, and inputs address data indicating an address in the memory cell array at which the storage data is input or output, the terminal including: a first terminal that inputs a first part of the address data; and a second terminal that inputs a second part of the address data, wherein the second part of the address data is included of the entire remaining portion of the address data not including the first part of the address data; a first internal address line and a second internal address line to which the address data is supplied; and a switch that couples the first part of the address data to one of the first internal address line or the second internal address line in accordance with predetermined switch information, while coupling the second part of the address data to the other one of the first inType: GrantFiled: November 20, 2007Date of Patent: January 5, 2010Assignee: Spansion LLCInventors: Kazuhiro Kurihara, Nobutaka Taniguchi
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Publication number: 20090300275Abstract: A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among sectors during erasing the data in the first sector, said pair of sectors being the first sector and the second sector; and an SRAM array (storage) (30) retaining the data of the second sector. The present invention can provide a semiconductor device in which a reduced number of sector select circuits is used so that the area of memory cell array can be reduced and provide a method of controlling the semiconductor device.Type: ApplicationFiled: June 25, 2009Publication date: December 3, 2009Inventors: Hiroki MURAKAMI, Kazuhiro KURIHARA
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Publication number: 20090279358Abstract: A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among sectors during erasing the data in the first sector, said pair of sectors being the first sector and the second sector; and an SRAM array (storage) (30) retaining the data of the second sector. The present invention can provide a semiconductor device in which a reduced number of sector select circuits is used so that the area of memory cell array can be reduced and provide a method of controlling the semiconductor device.Type: ApplicationFiled: July 23, 2009Publication date: November 12, 2009Inventors: Hiroki MURAKAMI, Kazuhiro KURIHARA
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Patent number: 7606068Abstract: A core-based multi-bit memory (400) having a dual-bit dynamic referencing architecture (408, 410) fabricated on the memory core (401). A first reference array (408) and a second reference array (410) are fabricated on the memory core (401) such that a reference cell pair (185) comprising one cell (182) of the first reference array (408) and a corresponding cell (184) of the second reference array (410) are read and averaged to provide a reference voltage for reading a data array(s).Type: GrantFiled: January 22, 2008Date of Patent: October 20, 2009Assignee: Spansion LLCInventors: Ming-Huei Shieh, Kazuhiro Kurihara
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Patent number: 7606085Abstract: The present invention is a semiconductor device including: a resistor R11 (first resistor part) and an FET 15 (second resistor part) connected in series between a power supply Vcc (first power supply) and ground (second power supply); an output node N11 provided between the resistor R11 and FET 15 and used for outputting a reference voltage; a feedback node N12 provided between the power supply Vcc and the ground; and a voltage control circuit (19) that maintains a voltage of the feedback node N12 at a constant level by using the reference voltage of the output node N11 and the voltage of the feedback node N12. The present invention can provide a semiconductor device having a reference voltage generating circuit capable of generating the reference voltage that does not greatly depend on a power supply voltage and its control method.Type: GrantFiled: August 8, 2006Date of Patent: October 20, 2009Assignee: Spansion LLCInventors: Hiroaki Wada, Kazuhiro Kurihara
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Patent number: 7573743Abstract: A semiconductor device includes: a first sector (12) having data that are all to be erased and having flash memory cells; a second sector (14) having data that are all to be retained and having flash memory cells; a sector select circuit (16) selecting a pair of sectors from among sectors during erasing the data in the first sector, said pair of sectors being the first sector and the second sector; and an SRAM array (storage) (30) retaining the data of the second sector. The present invention can provide a semiconductor device in which a reduced number of sector select circuits is used so that the area of memory cell array can be reduced and provide a method of controlling the semiconductor device.Type: GrantFiled: August 30, 2006Date of Patent: August 11, 2009Assignee: Spansion LLCInventors: Hiroki Murakami, Kazuhiro Kurihara
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Publication number: 20090034335Abstract: A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected. Each of the sectors includes a pull-up transistor that is driven by a corresponding one of the decoders via a corresponding one of global word lines connecting the sectors and drives one of the local word lines, and the pull-up transistor is kept OFF by the control signal.Type: ApplicationFiled: September 15, 2008Publication date: February 5, 2009Inventors: Yasuhiko Tanuma, Kazuhiro Kurihara
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Publication number: 20090016109Abstract: A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected. Each of the sectors includes a pull-up transistor that is driven by a corresponding one of the decoders via a corresponding one of global word lines connecting the sectors and drives one of the local word lines, and the pull-up transistor is kept OFF by the control signal.Type: ApplicationFiled: September 15, 2008Publication date: January 15, 2009Inventors: Yasuhiko Tanuma, Kazuhiro Kurihara
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Patent number: 7450434Abstract: A semiconductor device includes sectors having memory cells connected to local word lines, decoders selecting the sectors, and a circuit generating, in erasing of a selected sector, a control signal that causes a corresponding one of the decoders associated with the selected sector to be temporarily unselected. Each of the sectors includes a pull-up transistor that is driven by a corresponding one of the decoders via a corresponding one of global word lines connecting the sectors and drives one of the local word lines, and the pull-up transistor is kept OFF by the control signal.Type: GrantFiled: May 12, 2005Date of Patent: November 11, 2008Assignee: Spansion LLCInventors: Yasuhiko Tanuma, Kazuhiro Kurihara
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Publication number: 20080159011Abstract: The present invention provides a semiconductor device and a method of controlling the semiconductor device, the semiconductor device comprising: a memory cell array; a terminal that inputs or outputs storage data stored in the memory cell array, and inputs address data indicating an address in the memory cell array at which the storage data is input or output, the terminal comprising: a first terminal that inputs a first part of the address data; and a second terminal that inputs a second part of the address data, wherein the second part of the address data is comprised of the entire remaining portion of the address data not comprising the first part of the address data; a first internal address line and a second internal address line to which the address data is supplied; and a switch that couples the first part of the address data to one of the first internal address line or the second internal address line in accordance with predetermined switch information, while coupling the second part of the address daType: ApplicationFiled: November 20, 2007Publication date: July 3, 2008Inventors: Kazuhiro Kurihara, Nobutaka Taniguchi
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Publication number: 20080117678Abstract: A core-based multi-bit memory (400) having a dual-bit dynamic referencing architecture (408, 410) fabricated on the memory core (401). A first reference array (408) and a second reference array (410) are fabricated on the memory core (401) such that a reference cell pair (185) comprising one cell (182) of the first reference array (408) and a corresponding cell (184) of the second reference array (410) are read and averaged to provide a reference voltage for reading a data array(s).Type: ApplicationFiled: January 22, 2008Publication date: May 22, 2008Applicant: Spansion LLCInventors: Ming-Huei Shieh, Kazuhiro Kurihara
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Patent number: 7324374Abstract: A core-based multi-bit memory (400) having a dual-bit dynamic referencing architecture (408, 410) fabricated on the memory core (401). A first reference array (408) and a second reference array (410) are fabricated on the memory core (401) such that a reference cell pair (185) comprising one cell (182) of the first reference array (408) and a corresponding cell (184) of the second reference array (410) are read and averaged to provide a reference voltage for reading a data array(s).Type: GrantFiled: June 20, 2003Date of Patent: January 29, 2008Assignee: Spansion LLCInventors: Ming-Huei Shieh, Kazuhiro Kurihara
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Patent number: 7307894Abstract: The semiconductor device includes a memory cell array that includes memory cells for storing data and is managed on a sector basis, a memory that stores the information determining the activation status, a latch circuit that latches the activation information according to the information stored in the memory, and a circuit that latches the activation information according to the information stored in the memory in the latch circuit. The activation information according to the memory state of the memory is latched at the time of inputting a given command after activation, and it is thus possible to read the information stored in the memory and set the information in the latch circuit certainly.Type: GrantFiled: May 12, 2005Date of Patent: December 11, 2007Assignee: Spansion LLCInventors: Kazunari Kido, Kazuhiro Kurihara, Minoru Yamashita