Abstract: A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line charge and hold circuit which is operable to apply a read sense voltage (e.g., about 1.2 volts) to a bit line associated with the drain terminal of a cell of the flash array adjacent to the cell which is sensed, wherein the applied drain terminal voltage is substantially the same as the cell sense voltage (e.g., about 1.2 volts) applied to the drain terminal bit line of the selected memory cell to be sensed.

Abstract: A method and system are disclosed for memory cell soft program and soft program verify, to adjust, or correct the threshold voltage between a target minimum and maximum, which may be employed in association with a dual bit memory cell architecture. The method includes applying one reference voltage signal to the over erased core cell, and a different reference voltage signal to the reference cell, comparing the two currents produced by each, selectively verifying proper soft programming of one or more bits of the cell, determining that the dual bit memory cell is properly soft programmed. The method may also comprise selectively re-verifying proper soft programming of the cells after selectively soft programming at least one or more bits of the cell.

Abstract: System for boosting a signal for use in a memory device. The system includes a circuit for providing a boosted signal used to produce a word line signal in a memory device. The circuit includes a pre-charge stage that has an output terminal and is coupled to receive an address signal and a boost control signal. The pre-charge stage is operable to produce the boosted signal having a pre-charged level at the output terminal. The circuit also includes a boost stage that is coupled to receive the boost control signal and produce a boost activation signal at a boost stage output terminal that is coupled to the output terminal via a capacitive element. When the boost activation signal is active, the boosted signal is set to a selected boost level that is independent of supply voltage.

Abstract: A variable sector size for a flash memory device is disclosed. The total available memory of the flash memory device is divided into sub-units. Each sub-unit has a pre-decoder coupled with it to enable operations on the memory within that sub-unit. A sector size control register is coupled with pre-decoder enabling logic which is coupled with the pre-decoders. The sector size control register and pre-decoder enabling logic determines how many pre-decoders, and therefore how many sub-units, are activated at a given time for a given memory operation.

Abstract: A transmission circuit includes a baseband circuit, spreading section, multiplier, digital modulator, quadrature modulator, and antenna. The baseband circuit generates and outputs at least one transmission data constituted by first and second channel data. The spreading section spreads the transmission data with a spreading code that differs for each transmission channel. The multiplier respectively weights the amplitudes of the first and second channel data by using a combination of two gain factors determined by a transmission data rate. The digital modulator digitally modulates the first and second channel data whose amplitudes are weighted by the multiplier. The quadrature modulator quadrature-modulates the digitally modulated first and second channel data and outputs the data as a transmission signal. The antenna emits the transmission signal output from the quadrature modulator as a radio wave.

Abstract: A system is provided for reducing band-to-band tunneling current during Flash memory erase operations. The system includes a memory sector divided into (N) I/O subsectors, N being an integer, and a drain pump to generate power for associated erase operations within the N I/O subsectors. An erase sequencing subsystem generates N pulses to enable the erase operations within each of the N I/O subsectors in order to reduce band-to-band tunneling current provided by the drain pump.

Abstract: A memory device with a CAM cell and a read circuit are disclosed for reading a CAM cell using a boosted CAM gate voltage. The CAM read circuit comprises a voltage booster connected between the gate terminal of the CAM cell and a supply voltage, which provides a boosted voltage to the gate terminal of the CAM cell during a CAM read operation. Also disclosed is a method for reading a memory device CAM cell, wherein a boosted voltage is provided to the CAM cell gate.

Abstract: A decoder for decoding from two sides of a memory array. The decoder is positioned on two sides of the memory array. The decoder includes driver circuits that are connected to routing lines from the memory array. To reduce the size of the decoder, some of the routing lines extend from one side of the memory array and the remaining routing lines extend from the other side of the memory array.

Abstract: The present invention relates to flash memory systems and methods to determine the threshold voltage of core cells. In one exemplary system, there is provided a method of characterizing the high end of the threshold voltage distribution of an array of programmed cells. In accordance with the invention, an exemplary system and method are presented to apply a varying characterization signal operably through a high breakdown voltage periphery donut transistor and wordline drive transistors, which are driven into saturation by a boosted gate voltage which is higher than the applied varying characterization signal, in a manner which provides for the accurate determination of the VT of the core cells, through the comparison of the conduction in a reference cell to that of the conduction in a core cell produced by a varying characterization signal applied to the core cell gate.

Abstract: A pre-amplifier portion of a sense amplifier for a dual bank architecture simultaneous operation flash memory device is provided. The sense pre-amplifier circuit includes two inverting amplifiers, the second inverting amplifier providing a feedback loop for the first inverting amplifier. In addition, special “kicker” circuitry raises the sense pre-amplifier's input signal line to its operating level. The combination of inverting amplifiers, feedback loop and level raising circuitry is configured to provide higher bandwidths for the sense pre-amplifier to accommodate low capacitive loading resulting from a small memory bank. The combination is also configured to provide faster raising of the input signal line to operating level to accommodate high capacitive loading resulting from a large memory bank. The combination is also configured to provide increased signal margins at the output of the sense pre-amplifier.

Abstract: A sense amplifier output equalization circuit for a variable operating voltage high density flash memory device is disclosed. The equalization circuit compensates for the varying sensing speeds due to the varying operating voltages by variably adjusting the duration of an equalization pulse which is used to equalize the output stage of the sense amplifier to the input stage.

Abstract: When a received character data is decoded by a decoder 10, a word division circuit 21 divides the data into word units, and a voice storage circuit 22 outputs a voice data corresponding to the divided character data, and a D/A converter 30 converts it into an analog signal, and it is output from a speaker 40 as voice. Thereby, the character data is output as voice. An output from the decoder 10 is stored in a memory 50, and is displayed on an LCD 60 as a character. The LCD 60 receives a byte number of a word for every word from the word division circuit 21, and highlights it for every byte number.

Abstract: A dual bank flash memory device including a reference path equalization circuits is disclosed. In the device, each bank includes a read path with an electrical characteristic. The device further includes a reference circuit which comprises a reference cell and reference paths which also have an electrical characteristic. The reference equalization circuits are coupled with the reference circuit which equalizes the read path electrical characteristics with the reference path electrical characteristics.

Abstract: An equalization circuit for the power distribution paths of a high density flash memory device is disclosed. The equalization circuit matches the electrical characteristics of the reference path power distribution to those of the power distribution of the memory array wordlines so as to equalize the resistance and parasitic capacitance to the sense amplifiers.

Abstract: An equalization circuit for an address transition detector of a high density flash memory device is disclosed. The equalization circuit substantially equalizes the electrical characteristics of a particular signal path to those of another signal path wherein these signal paths transmit trigger signals which further generate other signals. The equalization ensures that resultant signals generated from the trigger signals which traverse these signal paths are generated in the same manner and with the same timing no matter which signal path the trigger signal travels down.

Abstract: An output buffer control circuit for a simultaneous operation flash memory device is disclosed. The output buffer control circuit receives signals indicating when an equalization or address transition detect phase of operation is happening and blocks the output enable input signal from reaching the output buffers of the memory device. This prevents the output buffers from switching.

Abstract: A memory device is disclosed that is operable with a supply voltage (Vcc) within an electronic system. The memory device is selected or placed in a standby mode by electric signals from the electronic system. The memory device includes an external voltage buffer circuit for buffering the electric signals that are generated by the electronic system using an external supply voltage. The external voltage buffer circuit includes a clamping circuit and an activation circuit. The clamping circuit generates a clamped signal with the external supply voltage and the supply voltage (Vcc). The activation circuit is responsive to the clamped signal and the electric signals and generates an output signal with the supply voltage (Vcc). The external voltage buffer circuit maintains low standby current during the standby mode since it operates with both the supply voltage (Vcc) and the external supply voltage.

Abstract: An AGC amplifier control circuit applying for both transmission and reception which the quantity of data memorizing in a memory is decreased and the address of the memory is simplified is provided. The AGC amplifier control circuit provides RF attenuators controlled in hysteresis and these RF attenuators are driven at the next gain renewing time of AGC amplifiers and provides attenuation controllers outputting the information whether the RF attenuators have a fixed attenuation quantity or not. In this construction of circuit, memories memorize the control voltage data of the gain of the AGC amplifiers with the relation of desired outputs, at the time when the RF attenuators are driven and have a fixed attenuation quantity, data conversion circuits convert the data to make the gain of the AGC amplifiers increase corresponding to these attenuation quantities.

Abstract: A power saving device of the present invention includes a first demodulation circuit for selectively demodulating modulated signals derived from at least two different systems. A second demodulation circuit demodulates only one of the modulated signals. A detection circuit detects a control signal out of any one of the modulated signals. A controller selects, based on the control signal detected by the detection circuit, either one of the first and second demodulation circuits while deactivating the other demodulation circuit. The device is capable of saving power during receipt of an FM (Frequency Modulation) modulated signal and preventing communication quality from being lowered when signal strength is low.

Abstract: A memory device is disclosed that is operated with a supply voltage (Vcc) and includes an output buffer circuit and an output buffer driver circuit. The output buffer circuit buffers data that is read out of the memory device and controls the output buffer driver circuit to generate data output signals using an external supply voltage (VccQ). The output buffer circuit controls the output buffer driver circuit with output signals generated with the supply voltage (Vcc) and an external supply voltage (VccQ). The output buffer driver circuit includes a p-channel pull-up transistor and an n-channel pull-down transistor that can be completely activated and deactivated by the output buffer circuit with the supply voltage (Vcc) and the external supply voltage (VccQ).