Patents by Inventor Kazushige Ayukawa
Kazushige Ayukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7554830Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.Type: GrantFiled: May 8, 2007Date of Patent: June 30, 2009Assignee: Renesas Technology Corp.Inventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 7280426Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.Type: GrantFiled: May 24, 2006Date of Patent: October 9, 2007Assignee: Renesas Technology CorporationInventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20070211543Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.Type: ApplicationFiled: May 8, 2007Publication date: September 13, 2007Inventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 7262983Abstract: A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.Type: GrantFiled: January 11, 2007Date of Patent: August 28, 2007Assignee: Renesas Techonology Corp.Inventors: Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata, Kazushige Ayukawa, Takayuki Kawahara
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Patent number: 7254680Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: GrantFiled: December 20, 2006Date of Patent: August 7, 2007Assignee: Renesas Technology Corp.Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Publication number: 20070153617Abstract: A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.Type: ApplicationFiled: January 11, 2007Publication date: July 5, 2007Inventors: Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata, Kazushige Ayukawa, Takayuki Kawahara
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Publication number: 20070101088Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: ApplicationFiled: December 20, 2006Publication date: May 3, 2007Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Patent number: 7184326Abstract: A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.Type: GrantFiled: November 8, 2005Date of Patent: February 27, 2007Assignee: Renesas Technology Corp.Inventors: Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata, Kazushige Ayukawa, Takayuki Kawahara
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Patent number: 7165151Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: GrantFiled: December 14, 2004Date of Patent: January 16, 2007Assignee: Renesas Technology Corp.Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Patent number: 7136978Abstract: A system and method are provided for using dynamic random access memory and flash memory. In one example, the memory system comprises a nonvolatile memory; synchronous dynamic random access memories; circuits including a control circuit which is coupled with the nonvolatile memory and the synchronous dynamic random access memories, and controls accesses to the nonvolatile memory and the synchronous dynamic random access memories; and a plurality of input/output terminals coupled with the circuits, wherein in data transfer from the nonvolatile memory to the synchronous dynamic random access memories, error corrected data is transferred.Type: GrantFiled: May 28, 2003Date of Patent: November 14, 2006Assignee: Renesas Technology CorporationInventors: Seiji Miura, Kazushige Ayukawa, Tetsuya Iwamura
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Publication number: 20060245281Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: ApplicationFiled: June 16, 2006Publication date: November 2, 2006Inventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20060221756Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.Type: ApplicationFiled: May 24, 2006Publication date: October 5, 2006Inventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 7076601Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: GrantFiled: November 14, 2003Date of Patent: July 11, 2006Assignee: Hitachi, Ltd.Inventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 7068562Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.Type: GrantFiled: June 13, 2005Date of Patent: June 27, 2006Assignee: Renesas Technology CorporationInventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20060062055Abstract: A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.Type: ApplicationFiled: November 8, 2005Publication date: March 23, 2006Inventors: Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata, Kazushige Ayukawa, Takayuki Kawahara
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Publication number: 20060041711Abstract: A memory system including large-capacity ROM and RAM in which high-speed reading and writing are enabled is provided. A memory system including a non-volatile memory (CHIP1), DRAM (CHIP3), a control circuit (CHIP2) and an information processing device (CHIP4) is configured. Data in FLASH is transferred to SRAM or DRAM in advance to speed up. Data transfer between the non-volatile memory (FLASH) and DRAM (CHIP3) can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. As data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction, the performance and the function of a mobile device can be enhanced.Type: ApplicationFiled: November 27, 2003Publication date: February 23, 2006Applicant: Renesas Technology CorporationInventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 6990037Abstract: A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.Type: GrantFiled: February 3, 2005Date of Patent: January 24, 2006Assignee: Renesas Technology CorporationInventors: Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata, Kazushige Ayukawa, Takayuki Kawahara
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Publication number: 20050232059Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.Type: ApplicationFiled: June 13, 2005Publication date: October 20, 2005Inventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 6952368Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.Type: GrantFiled: June 7, 2004Date of Patent: October 4, 2005Assignee: Renesas Technology CorporationInventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 6928512Abstract: A non-volatile memory, an SRAM, a DRAM and a control circuit are module-formed into a single packaged. The control circuit assigns addresses to the SRAM and addresses to the DRAM and data necessary to be held for a long period of time is saved in the SRAM. Two chips of DRAM are mapped to the same address space and refreshed alternately. The plural chips are arranged such that they are mutually laminated, and they are wired by means of a BGA or inter-chip bonding.Type: GrantFiled: June 6, 2002Date of Patent: August 9, 2005Assignees: Hitachi ULSI Systems Co, Ltd., Renesas Technology CorporationInventors: Kazushige Ayukawa, Seiji Miura, Tetsuya Iwamura, Kouichi Hoshi, Yoshikazu Saitou