Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.

Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

Abstract: A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or −1 arithmetic operation are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

Abstract: A memory macro is a combination of functional modules such as a main amplifier module, memory bank modules of which each memory bank operates independently, a power source circuit, etc. The storage capacity of the memory macro can be easily changed from a large capacity to a small one by changing the number of the memory bank modules. A control circuit in the memory bank modules of the memory macro has an additional address comparing function. Therefore, the same page can be accessed at high speed without providing any control circuit outside the memory macro. In addition, a module having a function such as a memory access sequence control is provided and, when memory access is made, identification information is issued at the time of inputting/outputting address or data. Therefore, high-speed memory access can be realized by checking the coincidence between the data and address with the ID and controlling the memory access sequence so that the address inputting order and data outputting order can be changed.

Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.

Abstract: A semiconductor device integrated on a chip includes a memory cell array, multiple processing elements and multiple data transfer circuits which transfer data between memory cells and the processing elements over read paths and write paths provided separately. The divide is capable of transferring data from memory cells to the processing elements and from the processing elements to memory cells concurrently over the read paths and write paths, respectively, so that faster image data processing is accomplished, and also capable of processing data on once-activated word lines successively thereby to reduce the number of times of driving of each word line so that the power consumption is reduced.

Abstract: A memory macro is a combination of functional modules such as a main amplifier module, memory bank modules of which each memory bank operates independently, a power source circuit, etc. The storage capacity of the memory macro can be easily changed from a large capacity to a small one by changing the number of the memory bank modules. A control circuit in the memory bank modules of the memory macro has an additional address comparing function. Therefore, the same page can be accessed at high speed without providing any control circuit outside the memory macro. In addition, a module having a function such as a memory access sequence control is provided and, when memory access is made, identification information is issued at the time of inputting/outputting address or data. Therefore, high-speed memory access can be realized by checking the coincidence between the data and address with the ID and controlling the memory access sequence so that the address inputting order and data outputting order can be changed.

Abstract: A semiconductor device integrated on a chip includes a memory cell array, multiple processing elements and multiple data transfer circuits which transfer data between memory cells and the processing elements over read paths and write paths provided separately. The divide is capable of transferring data from memory cells to the processing elements and from the processing elements to memory cells concurrently over the read paths and write paths, respectively, so that faster image data processing is accomplished, and also capable of processing data on once-activated word lines successively thereby to reduce the number of times of driving of each word line so that the power consumption is reduced.

Abstract: A semiconductor device integrated on a chip includes a memory cell array, multiple processing elements and multiple data transfer circuits which transfer data between memory cells and the processing elements over read paths and write paths provided separately. The divide is capable of transferring data from memory cells to the processing elements and from the processing elements to memory cells concurrently over the read paths and write paths, respectively, so that faster image data processing is accomplished, and also capable of processing data on once-activated word lines successively thereby to reduce the number of times of driving of each word line so that the power consumption is reduced.

Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.

Abstract: A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.

Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.

Abstract: A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

Abstract: A semiconductor device integrated on a chip includes a memory cell array, multiple processing elements and multiple data transfer circuits which transfer data between memory cells and the processing elements over read paths and write paths provided separately. The divide is capable of transferring data from memory cells to the processing elements and from the processing elements to memory cells concurrently over the read paths and write paths, respectively, so that faster image data processing is accomplished, and also capable of processing data on once-activated word lines successively thereby to reduce the number of times of driving of each word line so that the power consumption is reduced.

Abstract: A semiconductor device integrated on a chip includes a memory cell array, multiple processing elements and multiple data transfer circuits which transfer data between memory cells and the processing elements over read paths and write paths provided separately. The device is capable of transferring data from memory cells to the processing elements and from the processing elements to memory cells concurrently over the read paths and write paths, respectively, so that faster image data processing is accomplished. The device is also capable of processing data on once-activated word lines successively thereby reducing the number of times each word line is driven so that the power consumption is reduced.