Patents by Inventor Kazushige Ayukawa
Kazushige Ayukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6587393Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: GrantFiled: May 9, 2002Date of Patent: July 1, 2003Assignee: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou
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Patent number: 6584033Abstract: A memory macro is a combination of functional modules such as a main amplifier module, memory bank modules of which each memory bank operates independently, a power source circuit, etc. The storage capacity of the memory macro can be easily changed from a large capacity to a small one by changing the number of the memory bank modules. A control circuit in the memory bank modules of the memory macro has an additional address comparing function. Therefore, the same page can be accessed at high speed without providing any control circuit outside the memory macro. In addition, a module having a function such as a memory access sequence control is provided and, when memory access is made, identification information is issued at the time of inputting/outputting address or data. Therefore, high-speed memory access can be realized by checking the coincidence between the data and address with the ID and controlling the memory access sequence so that the address inputting order and data outputting order can be changed.Type: GrantFiled: April 24, 2002Date of Patent: June 24, 2003Assignee: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Takao Watanabe, Susumu Narita
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Patent number: 6574700Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: GrantFiled: November 8, 2001Date of Patent: June 3, 2003Assignee: Hitachi, Ltd.Inventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20030086288Abstract: A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.Type: ApplicationFiled: November 5, 2002Publication date: May 8, 2003Inventors: Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata, Kazushige Ayukawa, Takayuki Kawahara
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Patent number: 6542957Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: GrantFiled: November 8, 2001Date of Patent: April 1, 2003Assignee: Hitachi, Ltd.Inventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20020199056Abstract: A non-volatile memory, an SRAM, a DRAM and a control circuit are module-formed into a single packaged. The control circuit assigns addresses to the SRAM and addresses to the DRAM and data necessary to be held for a long period of time is saved in the SRAM. Two chips of DRAM are mapped to the same address space and refreshed alternately. The plural chips are arranged such that they are mutually laminated, and they are wired by means of a BGA or inter-chip bonding.Type: ApplicationFiled: June 7, 2002Publication date: December 26, 2002Applicant: Hitachi, Ltd. and Hitachi ULSI Systems Co., Ltd.Inventors: Kazushige Ayukawa, Seiji Miura, Tetsuya Iwamura, Kouichi Hoshi, Yoshikazu Saitou
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Publication number: 20020185337Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.Type: ApplicationFiled: June 10, 2002Publication date: December 12, 2002Applicant: Hitachi, Ltd.Inventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20020131318Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: ApplicationFiled: May 9, 2002Publication date: September 19, 2002Inventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou
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Publication number: 20020118591Abstract: A memory macro is a combination of functional modules such as a main amplifier module, memory bank modules of which each memory bank operates independently, a power source circuit, etc. The storage capacity of the memory macro can be easily changed from a large capacity to a small one by changing the number of the memory bank modules. A control circuit in the memory bank modules of the memory macro has an additional address comparing function. Therefore, the same page can be accessed at high speed without providing any control circuit outside the memory macro. In addition, a module having a function such as a memory access sequence control is provided and, when memory access is made, identification information is issued at the time of inputting/outputting address or data. Therefore, high-speed memory access can be realized by checking the coincidence between the data and address with the ID and controlling the memory access sequence so that the address inputting order and data outputting order can be changed.Type: ApplicationFiled: April 24, 2002Publication date: August 29, 2002Applicant: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Takao Watanabe, Susumu Narita
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Patent number: 6430089Abstract: A semiconductor device integrated on a chip includes a memory cell array, multiple processing elements and multiple data transfer circuits which transfer data between memory cells and the processing elements over read paths and write paths provided separately. The divide is capable of transferring data from memory cells to the processing elements and from the processing elements to memory cells concurrently over the read paths and write paths, respectively, so that faster image data processing is accomplished, and also capable of processing data on once-activated word lines successively thereby to reduce the number of times of driving of each word line so that the power consumption is reduced.Type: GrantFiled: December 21, 2000Date of Patent: August 6, 2002Assignee: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Takao Watanabe, Yoshinobu Nakagome
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Publication number: 20020103961Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: ApplicationFiled: March 20, 2002Publication date: August 1, 2002Applicant: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Patent number: 6411561Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: GrantFiled: July 3, 2001Date of Patent: June 25, 2002Assignee: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou
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Patent number: 6404694Abstract: A memory macro is a combination of functional modules such as a main amplifier module, memory bank modules of which each memory bank operates independently, a power source circuit, etc. The storage capacity of the memory macro can be easily changed from a large capacity to a small one by changing the number of the memory bank modules. A control circuit in the memory bank modules of the memory macro has an additional address comparing function. Therefore, the same page can be accessed at high speed without providing any control circuit outside the memory macro. In addition, a module having a function such as a memory access sequence control is provided and, when memory access is made, identification information is issued at the time of inputting/outputting address or data. Therefore, high-speed memory access can be realized by checking the coincidence between the data and address with the ID and controlling the memory access sequence so that the address inputting order and data outputting order can be changed.Type: GrantFiled: April 5, 2001Date of Patent: June 11, 2002Assignee: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Takao Watanabe, Susumu Narita
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Publication number: 20020065665Abstract: In a system that decompresses data compressed in compliance with the MPEG or JPEG standard, a buffer memory (603) to store values computed during decompression of the compressed data is split to plural banks (BNK); each of the banks is provided with an all-zero flag (AZF) indicating whether data within the bank is all “0”s; when data to be written to a bank is all “0”s, the all-zero flag is set without performing actual writing to the buffer memory; and during data reading, the flag is sensed to see if data within the bank is all “0”s, at which time reading from the buffer memory is omitted.Type: ApplicationFiled: October 16, 2001Publication date: May 30, 2002Applicant: Hitachi, Ltd.Inventors: Hiroyuki Hamasaki, Takashi Miyamoto, Hiroshi Takeda, Jun Sato, Kenichiro Omura, Kazushige Ayukawa
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Patent number: 6392950Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: GrantFiled: June 29, 2001Date of Patent: May 21, 2002Assignee: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou
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Publication number: 20020053001Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: ApplicationFiled: November 8, 2001Publication date: May 2, 2002Applicant: Hitachi, Ltd.Inventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 6381671Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: GrantFiled: June 29, 1999Date of Patent: April 30, 2002Assignee: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Publication number: 20020035662Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: ApplicationFiled: November 8, 2001Publication date: March 21, 2002Applicant: Hitachi, Ltd.Inventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20020023197Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: ApplicationFiled: August 20, 2001Publication date: February 21, 2002Applicant: Hitachi, Ltd.Inventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20020009834Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.Type: ApplicationFiled: September 28, 2001Publication date: January 24, 2002Applicant: Hitachi, Ltd.Inventors: Takao Watanabe, Kazushige Ayukawa, Ryo Fujita, Kazumasa Yanagisawa