Patents by Inventor Kazushige Ayukawa
Kazushige Ayukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050146960Abstract: A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.Type: ApplicationFiled: February 3, 2005Publication date: July 7, 2005Inventors: Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata, Kazushige Ayukawa, Takayuki Kawahara
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Publication number: 20050128853Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: ApplicationFiled: January 19, 2005Publication date: June 16, 2005Inventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou
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Patent number: 6894912Abstract: A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.Type: GrantFiled: January 21, 2004Date of Patent: May 17, 2005Assignee: Renesas Technology CorporationInventors: Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata, Kazushige Ayukawa, Takayuki Kawahara
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Publication number: 20050099876Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: ApplicationFiled: December 14, 2004Publication date: May 12, 2005Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Patent number: 6847575Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: GrantFiled: April 11, 2003Date of Patent: January 25, 2005Assignee: Renesas Technology Corp.Inventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou
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Patent number: 6847578Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: GrantFiled: December 9, 2003Date of Patent: January 25, 2005Assignee: Renesas Technology Corp.Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Publication number: 20040223366Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.Type: ApplicationFiled: June 7, 2004Publication date: November 11, 2004Applicant: Renesas Technology Corp.Inventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 6791877Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.Type: GrantFiled: June 10, 2002Date of Patent: September 14, 2004Assignee: Renesas Technology CorporationInventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20040151013Abstract: A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.Type: ApplicationFiled: January 21, 2004Publication date: August 5, 2004Applicant: Renesas Technology Corp.Inventors: Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata, Kazushige Ayukawa, Takayuki Kawahara
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Publication number: 20040114451Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: ApplicationFiled: December 9, 2003Publication date: June 17, 2004Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Publication number: 20040095818Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: ApplicationFiled: November 14, 2003Publication date: May 20, 2004Applicant: Hitachi, Ltd.Inventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 6721194Abstract: A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.Type: GrantFiled: November 5, 2002Date of Patent: April 13, 2004Assignee: Renesas Technology Corp.Inventors: Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata, Kazushige Ayukawa, Takayuki Kawahara
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Patent number: 6708249Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.Type: GrantFiled: March 20, 2002Date of Patent: March 16, 2004Assignee: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
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Publication number: 20040049629Abstract: A system and method are provided for using dynamic random access memory and flash memory. In one example, the memory system comprises a nonvolatile memory; synchronous dynamic random access memories; circuits including a control circuit which is coupled with the nonvolatile memory and the synchronous dynamic random access memories, and controls accesses to the nonvolatile memory and the synchronous dynamic random access memories; and a plurality of input/output terminals coupled with the circuits, wherein in data transfer from the nonvolatile memory to the synchronous dynamic random access memories, error corrected data is transferred.Type: ApplicationFiled: May 28, 2003Publication date: March 11, 2004Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Seiji Miura, Kazushige Ayukawa, Tetsuya Iwamura
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Patent number: 6697906Abstract: A semiconductor device is connected to a CPU, a memory and I/O devices to serve as a data transfer bridge for efficient data transfer between the memory and the I/O devices. A CPU interface and a plurality of I/O interfaces included in a bridge chip are connected through an internal bus to a memory interface included in the bridge chip. Each I/O interface has a read/write buffer and a DMAC. An arbiter included in the bridge chip determines a bus master for which data transfer is permitted in response to requests for data transfer from each of the CPU interface and the DMAC to the memory. Each of the I/O interfaces has a control function to skip part of areas in the memory when transferring data between the memory and the I/O interface.Type: GrantFiled: April 28, 2000Date of Patent: February 24, 2004Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Kazushige Ayukawa, Jun Sato, Takashi Miyamoto, Kenichiro Omura, Hiroyuki Hamasaki, Hiroshi Takeda, Makoto Takano, Isamu Mochizuki, Yasuhiko Hoshi, Kazuhiro Hirade, Ryuichi Murashima
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Patent number: 6675269Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: GrantFiled: February 4, 2003Date of Patent: January 6, 2004Assignee: Hitachi, Ltd.Inventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20030206478Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: ApplicationFiled: April 11, 2003Publication date: November 6, 2003Applicant: Hitachi, Ltd.Inventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou
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Patent number: 6609236Abstract: A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module.Type: GrantFiled: September 28, 2001Date of Patent: August 19, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takao Watanabe, Kazushige Ayukawa, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka
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Publication number: 20030126392Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: ApplicationFiled: February 4, 2003Publication date: July 3, 2003Applicant: Hitachi, Ltd.Inventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 6587934Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: GrantFiled: August 20, 2001Date of Patent: July 1, 2003Assignee: Hitachi, Ltd.Inventors: Seiji Miura, Kazushige Ayukawa