Patents by Inventor Kazutaka Miyano
Kazutaka Miyano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190272862Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.Type: ApplicationFiled: May 22, 2019Publication date: September 5, 2019Inventors: Yoshiya Komatsu, Kazutaka Miyano, Atsuko Momma
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Patent number: 10403340Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.Type: GrantFiled: February 7, 2018Date of Patent: September 3, 2019Assignee: Micron Technology, Inc.Inventors: Yoshiya Komatsu, Kazutaka Miyano, Atsuko Momma
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Publication number: 20190244644Abstract: An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device through various modes of operation. A clock enable control circuit is provided to control the input of a delay locked loop circuit to provide a locked condition based on a particular type of command input and the state of various control signals to allow for multiple locking conditions and adjustments based on a length of a clock cycle of the internal clock signal.Type: ApplicationFiled: February 7, 2018Publication date: August 8, 2019Inventors: Yoshiya Komatsu, Kazutaka Miyano, Atsuko Momma
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Publication number: 20190181847Abstract: Apparatuses and methods for data transmission offset values in burst transmissions. An example apparatus may include offset logic configured to provide offset values associated with a receiver circuit of a memory device coupled to a signal line. The offset values are based on individual transition threshold voltages biases of sample circuits of the receiver circuit. The example apparatus may further include an input/output (I/O) circuit comprising a driver circuit. The driver circuit configured to receive a logic signal and the offset values and to provide an output signal to the signal line based on the logic signal and to adjust voltages of the output signal based on the offset values.Type: ApplicationFiled: December 12, 2017Publication date: June 13, 2019Applicant: Micron Technology, Inc.Inventors: Yasuo Satoh, Kazutaka Miyano
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Patent number: 10290336Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.Type: GrantFiled: May 15, 2017Date of Patent: May 14, 2019Assignee: Micron Technology, Inc.Inventors: Shuichi Ishibashi, Kazutaka Miyano, Hiroki Fujisawa
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Publication number: 20180358064Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.Type: ApplicationFiled: August 21, 2018Publication date: December 13, 2018Applicant: Micron Technology, Inc.Inventors: Shuichi Ishibashi, Kazutaka Miyano, Hiroki Fujisawa
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Publication number: 20180286470Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.Type: ApplicationFiled: June 5, 2018Publication date: October 4, 2018Applicant: Micron Technology, Inc.Inventors: Kazutaka Miyano, Atsuko Momma
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Patent number: 9997220Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.Type: GrantFiled: August 22, 2016Date of Patent: June 12, 2018Assignee: Micron Technology, Inc.Inventors: Kazutaka Miyano, Atsuko Momma
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Publication number: 20180053538Abstract: Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a timing circuit that includes a divider circuit that receives a first clock signal having a first frequency and provides a complementary pair of second and third clock signals having a second frequency that is half the first frequency; a first delay circuit that receives the second clock signal and provides a delayed second clock signal responsive to the second clock signal; and a second delay circuit that receives the third clock signal and provides a delayed third clock signal responsive to the third clock signal. The timing circuit receives a first signal, latches the first signal responsive to the delayed second clock signal to provide a second signal and latches the second signal responsive to either the second clock signal or the third clock signal responsive to latency information.Type: ApplicationFiled: August 22, 2016Publication date: February 22, 2018Applicant: Micron Technology, Inc.Inventors: Kazutaka Miyano, Atsuko Momma
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Patent number: 9865317Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.Type: GrantFiled: April 26, 2016Date of Patent: January 9, 2018Assignee: Micron Technology, Inc.Inventors: Shuichi Ishibashi, Kazutaka Miyano, Hiroki Fujisawa
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Publication number: 20170309323Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.Type: ApplicationFiled: May 15, 2017Publication date: October 26, 2017Applicant: Micron Technology, Inc.Inventors: Shuichi Ishibashi, Kazutaka Miyano, Hiroki Fujisawa
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Publication number: 20170309320Abstract: Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that provides a reference clock signal and a system clock signal based on an external clock signal; a command decoder that latches command signals with the system clock signal and further provides a signal based on the command signals; and a command delay adjustment circuit including: a clock synchronizing circuit that receives the signal, latches the signal with the system clock signal and provides a clock-synchronized read signal responsive to a shift cycle parameter.Type: ApplicationFiled: April 26, 2016Publication date: October 26, 2017Applicant: Micron Technology, Inc.Inventors: Shuichi Ishibashi, Kazutaka Miyano, Hiroki Fujisawa
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Patent number: 9570149Abstract: An output signal generation device in accordance with disclosed embodiments includes: a phase adjustment unit that generates an output signal on the basis of an input signal and is capable of executing an adjustment operation of setting the phase difference between the input signal and the output signal to a predetermined value; a holding unit that holds a reference voltage; a comparison voltage generation unit that generates a comparison voltage that is dependent on a power supply voltage; and a control unit that intermittently compares the comparison voltage with the reference voltage held in the holding unit, causes the phase adjustment circuit to execute the adjustment operation when the comparison result satisfies a predetermined condition representing a variation in the power supply voltage, and changes the reference voltage held in the holding unit in accordance with the power supply voltage.Type: GrantFiled: January 15, 2014Date of Patent: February 14, 2017Assignee: LONGITUDE SEMICONDUCTOR S.A.R.L.Inventor: Kazutaka Miyano
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Patent number: 9531363Abstract: Methods and apparatus including a latency control circuit are described. An example apparatus includes a delay line circuit configured to delay a clock signal, and a latch control circuit configured to receive the clock signal and the delayed clock signal. The latch control circuit is configured to provide first control signals based on a count associated with the first clock signal. The latch control circuit is further configured to provide second control signals based on the count associated with the first clock signal. The second clock signals are delayed relative to the first clock signals by an amount substantially equal to a delay between the clock signal and the delayed clock signal. The example apparatus further includes a latch circuit configured to latch an input signal responsive to the first control signals. The latch circuit is further configured to provide the latched signal to an output responsive to the second control signals.Type: GrantFiled: April 28, 2015Date of Patent: December 27, 2016Assignee: Micron Technology, Inc.Inventor: Kazutaka Miyano
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Publication number: 20160322964Abstract: Methods and apparatus including a latency control circuit are described. An example apparatus includes a delay line circuit configured to delay a clock signal, and a latch control circuit configured to receive the clock signal and the delayed clock signal. The latch control circuit is configured to provide first control signals based on a count associated with the first clock signal. The latch control circuit is further configured to provide second control signals based on the count associated with the first clock signal. The second clock signals are delayed relative to the first clock signals by an amount substantially equal to a delay between the clock signal and the delayed clock signal. The example apparatus further includes a latch circuit configured to latch an input signal responsive to the first control signals. The latch circuit is further configured to provide the latched signal to an output responsive to the second control signals.Type: ApplicationFiled: April 28, 2015Publication date: November 3, 2016Inventor: Kazutaka Miyano
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Patent number: 9438251Abstract: A method for generating an internal clock signal by a clock generating circuit, including generating the internal clock signal based on an external clock signal, adjusting a phase of the internal clock signal by using a phase control value to synchronize with a phase of the external clock signal based on a phase difference between the external clock signal and the internal clock signal, switching operation modes including a first operation mode in which a phase of the internal clock signal is controlled at a predetermined cycle by updating the phase control value and a second operation mode in which a phase of the internal clock signal is fixed by fixing the phase control value, and the switching includes switching from the second operation mode to the first operation mode in response to a trigger signal.Type: GrantFiled: April 6, 2015Date of Patent: September 6, 2016Assignee: PS4 LUXCO S.A.R.L.Inventor: Kazutaka Miyano
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Publication number: 20150364181Abstract: An output signal generation device in accordance with disclosed embodiments includes: a phase adjustment unit that generates an output signal on the basis of an input signal and is capable of executing an adjustment operation of setting the phase difference between the input signal and the output signal to a predetermined value; a holding unit that holds a reference voltage; a comparison voltage generation unit that generates a comparison voltage that is dependent on a power supply voltage; and a control unit that intermittently compares the comparison voltage with the reference voltage held in the holding unit, causes the phase adjustment circuit to execute the adjustment operation when the comparison result satisfies a predetermined condition representing a variation in the power supply voltage, and changes the reference voltage held in the holding unit in accordance with the power supply voltage.Type: ApplicationFiled: January 15, 2014Publication date: December 17, 2015Applicant: PS4 Luxco S.a.r.l.Inventor: Kazutaka Miyano
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Patent number: 9196349Abstract: A device includes an output circuit, a DLL (Delay Locked Loop) circuit including a first delay line receiving a first clock signal and outputting, in response to receiving the clock signal, a second clock signal supplied to the output circuit, and an ODT (On Die Termination) circuit receiving an ODT activation signal and outputting, in response to receiving the ODT activation signal, an ODT output signal supplied to the output circuit to set the output circuit in a resistance termination state, and the ODT circuit including a second delay line configured to be set by the DLL circuit in an equivalent delay amount that is equivalent to a delay amount of the first delay line, the ODT output signal being, in a first time-period during which the ODT activation signal is in an active state, generated by being conveyed via the second delay line in which the equivalent delay amount has been set.Type: GrantFiled: July 25, 2014Date of Patent: November 24, 2015Assignee: MICRON TECHNOLOGY, INC.Inventors: Kazutaka Miyano, Hiroki Fujisawa
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Publication number: 20150214962Abstract: A method for generating an internal clock signal by a clock generating circuit, including generating the internal clock signal based on an external clock signal, adjusting a phase of the internal clock signal by using a phase control value to synchronize with a phase of the external clock signal based on a phase difference between the external clock signal and the internal clock signal, switching operation modes including a first operation mode in which a phase of the internal clock signal is controlled at a predetermined cycle by updating the phase control value and a second operation mode in which a phase of the internal clock signal is fixed by fixing the phase control value, and the switching includes switching from the second operation mode to the first operation mode in response to a trigger signal.Type: ApplicationFiled: April 6, 2015Publication date: July 30, 2015Inventor: Kazutaka Miyano
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Patent number: 9053779Abstract: A semiconductor device includes a first input terminal configured to receive a first clock signal, first control terminals configured to receive first control signals respectively, an output terminal, first inverters each including an input node coupled to the first input terminal, a control node coupled to a corresponding one of the first control terminals and an output node coupled to the output terminal, each of the first inverters being configured to be controlled to output an inverted first clock signal to the output terminal in response to a corresponding one of the first control signals supplied to a corresponding one of the control nodes, and an additional first inverter including an input node coupled to the first input terminal and an output node coupled to the output terminal, the additional first inverter being free from any other control nodes to output an inverted first clock signal to the output terminal.Type: GrantFiled: January 31, 2014Date of Patent: June 9, 2015Assignee: Micron Technology, Inc.Inventors: Kazutaka Miyano, Ryuji Takishita, Takeshi Konno