Patents by Inventor Kazutaka Miyano

Kazutaka Miyano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6166669
    Abstract: A noise-immune electronic circuit includes an input circuit for receiving an inbound signal through an input transmission line and comparing the inbound signal with a decision threshold to produce input data of the electronic circuit having one of predefined discrete levels depending on relative magnitudes of the inbound signal and the decision threshold and an output circuit for receiving output data of the electronic circuit and producing therefrom an outbound signal and forwarding the outbound signal onto an output transmission line. The input and output transmission lines are inductively coupled together so that a noise is introduced to the received inbound signal when a voltage transition occurs in the forwarded outbound signal.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: December 26, 2000
    Assignee: NEC Corporation
    Inventor: Kazutaka Miyano
  • Patent number: 6078200
    Abstract: A clock signal generator includes a phase shifter for generating four clock signals having phases consecutively shifted from one another by 90 degrees based on an external clock signal, a mixer for mixing two of the four clock signals to output an internal clock signal, and an initializing circuit for selecting consecutively one and another of the four clock signals as an internal clock signal in an initializing period. A phase comparator compares the internal clock signal against the external clock signal in the initializing period to determine which of the internal clock signal and the external clock signal leads. The initializing circuit reduces the time length for locking of the internal clock signal to the external clock signal in an operational period of the mixer.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: June 20, 2000
    Assignee: NEC Corporation
    Inventor: Kazutaka Miyano
  • Patent number: 6021080
    Abstract: The voltage reducing circuit 40 comprises driver circuits 21 to 24 corresponding to the memory cell arrays 11 to 14, and only one control circuit 20. Each of the driver circuit changes an external power source voltage VEXT into the internal power source voltage INTS and supplies the internal power source voltage INTS to one corresponding memory cell array according to a control signal C1. The control circuit commonly receives the internal power source voltage INTS and generates the control signal in response to the level of the internal power source voltage. The control signal is commonly provided to the driver circuits.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: February 1, 2000
    Assignee: NEC Corporation
    Inventor: Kazutaka Miyano