Abstract: A semiconductor device which has a duty detection circuit that detects a duty error in an internal clock synchronized with an external clock and is capable of performing accurate duty measurement. A first capacitor is coupled to a first node and a first current source coupled to a second node. A first switch is coupled between the first and second nodes. A second switch is coupled between a voltage line and the first node and a third switch is coupled between the voltage line and the second node, the third switch being rendered conductive while the second switch is in a conductive state. A second current source is coupled to a third node, with a fourth switch coupled between the first and the third nodes. A fifth switch is coupled between the voltage line and the third node, the fifth switch being rendered conductive while the second switch is in the conductive state.

Abstract: A delay circuit generates an internal clock signal or a second clock signal by delaying an external clock signal. A detection-potential generation circuit included in a phase-difference determination circuit generates a detection potential corresponding to a difference between a timing of an active edge of an internal clock signal or a third clock signal and a timing of the target external clock signal in a first node. A reference-potential generation circuit included in the phase-difference determination circuit generates a reference potential in a second node. A phase control circuit delays the second clock signal according to the detection potential. At this time, when the detection potential is higher than the reference potential, an adjustment amount of the second clock signal per adjustment changes.

Abstract: To include a first level shift circuit that converts a first internal clock signal having an amplitude value of a first voltage into a second internal clock signal having an amplitude value of a second voltage, a second level shift circuit that converts a first internal data signal having the amplitude value of the first voltage into a second internal data signal having the amplitude value of the second voltage, a clock dividing circuit that generates third and fourth internal clock signals, which are complementary signals, based on the second internal clock signal, and an output circuit that outputs external data signals continuously from a data output terminal in synchronization with the third and fourth internal clock signals based on the second internal data signal. According to the present invention, because a level shift of a signal is performed before it is input to the output circuit, there occurs no skew in output data.

Abstract: To include a phase determining circuit that generates a first phase determination signal, a sampling circuit that samples the first phase determination signal and generates a second phase determination signal based on the sampled first phase determination signal, and a clock generating unit that generates an internal clock signal based on the second phase determination signal. The sampling circuit includes a continuity determining circuit that fixes the second phase determination signal when a logic level of the first phase determination signal changes within a sampling cycle, an initial operation circuit that fixes the second phase determination signal at a high level until when a third phase determination signal indicates a high level, and a disabling circuit that disables an operation of the continuity determining circuit after the third phase determination signal indicates a high level.

Abstract: A clock generating circuit includes a delay line that generates an internal clock signal, a phase-controlling unit that adjusts a phase of the internal clock signal by controlling the delay line, and a mode switching circuit that switches an operation mode of the phase-controlling unit. The phase-controlling unit has a first operation mode in which a phase of the internal clock signal is changed in synchronization with a sampling clock signal and a second operation mode in which the phase of the internal clock signal is fixed. The mode switching circuit shifts the phase-controlling unit to the first operation mode in response to a trigger signal, such as a refresh signal, and, shifts the phase-controlling unit to the second operation mode in a state where the internal clock signal attains a predetermined phase.

Abstract: A device includes a first circuit unit performing a detecting operation to detect a ratio of a first time period in which an input signal takes a first logic level to a second time period in which the input signal takes a second logic level. The first circuit unit includes a storing unit and storing a detection result of a detection thereby to the storing unit thereof. The device includes a first control circuit controlling the first circuit unit in response to the input signal. The device includes a current source circuit coupled to the first control circuit at a first circuit node thereof. The device includes an initialization circuit performing an initializing operation to initialize the detection result of the storing unit of the first circuit unit.

Abstract: A clock control circuit includes a phase determination circuit that generates a first phase determination signal based on a phase of an external clock signal, a counter circuit that updates a count value based on a second phase determination signal for each sampling period, a delay line that generates an internal clock signal by delaying the external clock signal based on the count value, and an invalidation circuit that generates the second phase determination signal which is obtained by invalidating a change of the first phase determination signal within a same sampling period in response to a fact that the first phase determination circuit indicates a predetermined logical level.

Abstract: To provide a DLL circuit including: a first phase determination circuit that compares phases of rising edges of an external clock and a first internal clock; a second phase determination circuit that compares phases of falling edges of the external clock and the first internal clock; an adjusting unit that adjusts positions of active edges of internal clocks based on determination results; and a control circuit that sets one of adjustment amounts of the second and third internal clocks to a larger value than the other, in response to a fact that adjustment directions of the active edges of the second and third internal clocks are mutually the same. With this arrangement, a duty can be set nearer to 50% while performing phase adjustment. Accordingly, the time required to lock the DLL circuit can be shortened.

Abstract: A semiconductor device includes a first duty determining circuit (20) and a second duty determining circuit (30). The first duty determining circuit (20) determines a duty correction condition for an input signal in a first predetermined cycle longer than a cycle of the input signal to obtain a first determination result and updates the duty correction condition for the input signal on the basis of the first determination result. The second duty determining circuit (30) determines the duty correction condition for the input signal in a second predetermined cycle shorter than first predetermined cycle to obtain a second determination result and updates the duty correction condition for the input signal only when the second determination result is fixed during a predetermined period.

Abstract: A semiconductor chip includes a plurality of pads; a plurality of interface circuits connected with the plurality of pads, respectively; an internal circuit connected with the plurality of interface circuits; and a transfer circuit connecting the plurality of interface circuits with each other in response to a test mode signal. One of the plurality of pads is a selected pad when the pad is probed, at least one remaining pad is a non-selected pad, one of the plurality of interface circuits corresponding to the selected pad is a selected interface circuit, and at least one remaining interface circuit is a non-selected interface circuit. The internal circuit is tested by using the selected pad, the selected interface circuit, the transfer circuit, and the non-selected interface circuit without using the non-selected pads.

Abstract: A semiconductor chip includes a plurality of pads; a plurality of interface circuits connected with the plurality of pads, respectively; an internal circuit connected with the plurality of interface circuits; and a transfer circuit connecting the plurality of interface circuits with each other in response to a test mode signal. One of the plurality of pads is a selected pad when the pad is probed, at least one remaining pad is a non-selected pad, one of the plurality of interface circuits corresponding to the selected pad is a selected interface circuit, and at least one remaining interface circuit is a non-selected interface circuit. The internal circuit is tested by using the selected pad, the selected interface circuit, the transfer circuit, and the non-selected interface circuit without using the non-selected pads.

Abstract: A DLL (delay locked loop) circuit for outputting a phase lock signal having a predetermined phase relationship with an input signal. The DLL circuit has: a functional block having a constant-current source; and bias generator for generating a constant current source bias signal for controlling the constant current source of the functional block, the bias generator comprising a bias control which changes the bias signal according to the frequency of the input signal.

Abstract: In a duty ratio detecting apparatus, a duty ratio detecting circuit is constructed by first and second nodes, a load current supplying circuit for supplying first and second load currents to the first and second nodes, respectively, and a current switch connected to the first and second nodes. The current switch is operated in response to first and second complementary duty ratio signals. A duty ratio maintaining circuit is constructed by third and fourth nodes for receiving and maintaining voltages at the first and second nodes, respectively. A first switch is connected between the first and third nodes, and a second switch is connected between the second and fourth nodes. The load current supplying circuit is controlled by voltages at the third and fourth nodes.

Abstract: A voltage boosting circuit in which a changing rate of current is limited to reduce noise. An oscillator circuit sends a plurality of oscillating signals differing in edge timing from each other. An enable circuit counts the number of the edges of at least one of the oscillating signals from a start of a boosting operation, and generates an enable signal for instructing a boosting power control circuit to reduce the boosting power of the corresponding one of pumping circuits until the count value becomes a set value. The boosting power control circuit controls the boosting power of each pumping circuit in response to the enable signal. Each pumping circuit performs a boosting operation by charging and discharging a pumping capacitor by using the corresponding one of the oscillated signals. The pumping circuits generate a boosted voltage by combining their outputs signals.

Abstract: A voltage boosting circuit in which a changing rate of current is limited to reduce noise. An oscillator circuit sends a plurality of oscillating signals differing in edge timing from each other. An enable circuit counts the number of the edges of at least one of the oscillating signals from a start of a boosting operation, and generates an enable signal for instructing a boosting power control circuit to reduce the boosting power of the corresponding one of pumping circuits until the count value becomes a set value. The boosting power control circuit controls the boosting power of each pumping circuit in response to the enable signal. Each pumping circuit performs a boosting operation by charging and discharging a pumping capacitor by using the corresponding one of the oscillated signals. The pumping circuits generate a boosted voltage by combining their outputs signals.

Abstract: In a duty ratio detecting apparatus, a duty ratio detecting circuit is constructed by first and second nodes, a load current supplying circuit for supplying first and second load currents to the first and second nodes, respectively, and a current switch connected to the first and second nodes. The current switch is operated in response to first and second complementary duty ratio signals. A duty ratio maintaining circuit is constructed by third and fourth nodes for receiving and maintaining voltages at the first and second nodes, respectively. A first switch is connected between the first and third nodes, and a second switch is connected between the second and fourth nodes. The load current supplying circuit is controlled by voltages at the third and fourth nodes.

Abstract: A delay locked loop (DLL) circuit (10) can include first phase decision circuit (1), a second phase decision circuit (2), an arbitrary phase generator circuit (3), and a variable pulse width circuit (4). First phase decision circuit (1) may receive an external clock signal (D1) and an internal clock signal (D3) and may generate a phase decision signal (D4) that may indicate whether a first edge of internal clock signal (D3) is to be sped-up or delayed. Arbitrary phase generator circuit (3) may provide a phase shifted signal based on phase decision signal (D4). Second phase decision circuit (2) may receive external clock signal (D1) and internal clock signal (D3) and may generate a phase decision signal (D5) that may indicate whether a second edge of internal clock signal (D3) is to be sped-up or delayed. Variable pulse width circuit (4) may receive the phase shifted signal and delay a falling edge based on phase decision signal (D5).

Abstract: A delay locked loop (DLL) circuit (10) having an internal clock signal (D3) with positive and negative clock edges locked with an externally applied clock signal (D1) is provided. The DLL circuit (10) can include first phase decision circuit (1), a second phase decision circuit (2), an arbitrary phase generator circuit (3), and a variable pulse width circuit (4). First phase decision circuit (1) may receive external clock signal (D1) and internal clock signal (D3) and may generate a phase decision signal (D4) that may indicate whether a first edge of internal clock signal (D3) is to be sped-up or delayed. Arbitrary phase generator circuit (3) may provide a phase shifted signal based on phase decision signal (D4). Second phase decision circuit (2) may receive external clock signal (D1) and internal clock signal (D3) and may generate a phase decision signal (D5) that may indicate whether a second edge of internal clock signal (D3) is to be sped-up or delayed.

Abstract: Discloscd is a DLL (delay locked loop) circuit for outputting a phase lock signal having a predetermined phase relationship with an input signal. The DLL circuit has: a functional block having a constant-current source; and bias generation means for generating a constant current source bias signal for controlling the constant current source of the functional block, the bias generation means comprising bias control means which changes the bias signal according to the frequency of the input signal.

Abstract: A digital Delay-Locked Loop (DLL) circuit includes a phase locking unit, an adder, and a phase delay unit. The phase locking unit generates a first internal clock phase-locked with an external clock by adjusting a first digital phase control amount on the basis of a phase difference between an external clock and the first internal clock. The adder adds a predetermined phase control amount to the first digital phase control amount to output a second digital phase control amount when the first internal clock is generated by the phase locking unit. The phase delay unit generates a second internal clock delayed from the external clock by the predetermined control amount, on the basis of the second digital phase control amount from the adder.