Abstract: A device including input and output nodes, first and second input circuits coupled in parallel to each other between the input and output nodes. The first input circuit includes a first circuit unit coupled between the input and output nodes, the first circuit unit is configured to be activated when a first selection signal supplied thereto takes an active level and deactivated when the first selection signal takes an inactive level. The first circuit unit is configured to respond to a change of a control signal, which is received from a control circuit, from a first logic level to a second logic level and the first circuit unit is configured to change the first selection signal from the active level to the inactive level after a lapse of a first period.

Abstract: A clock generating circuit includes a delay line that generates an internal clock signal, a phase-controlling unit that adjusts a phase of the internal clock signal by controlling the delay line, and a mode switching circuit that switches an operation mode of the phase-controlling unit. The phase-controlling unit has a first operation mode in which a phase of the internal clock signal is changed in synchronization with a sampling clock signal and a second operation mode in which the phase of the internal clock signal is fixed. The mode switching circuit shifts the phase-controlling unit to the first operation mode in response to a trigger signal, such as a refresh signal, and, shifts the phase-controlling unit to the second operation mode in a state where the internal clock signal attains a predetermined phase.

Abstract: A device includes an output circuit, a DLL (Delay Locked Loop) circuit including a first delay line receiving a first clock signal and outputting, in response to receiving the clock signal, a second clock signal supplied to the output circuit, and an ODT (On Die Termination) circuit receiving an ODT activation signal and outputting, in response to receiving the ODT activation signal, an ODT output signal supplied to the output circuit to set the output circuit in a resistance termination state, and the ODT circuit including a second delay line configured to be set by the DLL circuit in an equivalent delay amount that is equivalent to a delay amount of the first delay line, the ODT output signal being, in a first time-period during which the ODT activation signal is in an active state, generated by being conveyed via the second delay line in which the equivalent delay amount has been set.

Abstract: A semiconductor device includes: an input node supplied with an input signal; an output node provided correspondingly to the input node; first and second input circuits coupled in parallel to each other between the input and output nodes; and a control circuit configured to control the first and second input circuits such that one of the first and second input circuits is switched over from an active state to an inactive state and the other of the first and second input circuits is switched over from an inactive state to an active state during the one of the first and second input circuits being still in the active state.

Abstract: A semiconductor device includes a first input terminal configured to receive a first clock signal, first control terminals configured to receive first control signals respectively, an output terminal, first inverters each including an input node coupled to the first input terminal, a control node coupled to a corresponding one of the first control terminals and an output node coupled to the output terminal, each of the first inverters being configured to be controlled to output an inverted first clock signal to the output terminal in response to a corresponding one of the first control signals supplied to a corresponding one of the control nodes, and an additional first inverter including an input node coupled to the first input terminal and an output node coupled to the output terminal, the additional first inverter being free from any other control nodes to output an inverted first clock signal to the output terminal.

Abstract: A semiconductor device with a clock control circuit that outputs an internal clock signal configured by delaying external clock signals based on at least a feedback clock signal; a plurality of output buffers that output data in synchronization with the internal clock signal; an output replica that is a replica of the output buffers and that generates the feedback clock signal in synchronization with the internal clock signal and supplies the feedback clock signal to the clock control circuit; and a clock tree that receives the internal clock signal from the clock control circuit and transmits the internal clock signal to the plurality of output buffers and the output replica such that signal line are substantially equal to one another.

Abstract: A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V2 from a first voltage V1; and a control circuit that generates the current control signal OVDR, makes a current that is flowed by the current mirror increase by a first transition of the current control signal OVDR, and makes the current that is flowed by the current mirror decrease by a second transition of the current control signal OVDR. The control circuit includes a slew-rate processing unit that makes a second slew rate of the current control signal OVDR related to the second transition be smaller than a first slew rate of the current control signal OVDR related to the first transition.

Abstract: A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V2 from a first voltage V1; and a control circuit that generates the current control signal OVDR, makes a current that is flowed by the current mirror increase by a first transition of the current control signal OVDR, and makes the current that is flowed by the current mirror decrease by a second transition of the current control signal OVDR. The control circuit includes a slew-rate processing unit that makes a second slew rate of the current control signal OVDR related to the second transition be smaller than a first slew rate of the current control signal OVDR related to the first transition.

Abstract: A delay circuit generates an internal clock signal or a second clock signal by delaying an external clock signal. A detection-potential generation circuit included in a phase-difference determination circuit generates a detection potential corresponding to a difference between a timing of an active edge of an internal clock signal or a third clock signal and a timing of the target external clock signal in a first node. A reference-potential generation circuit included in the phase-difference determination circuit generates a reference potential in a second node. A phase control circuit delays the second clock signal according to the detection potential. At this time, when the detection potential is higher than the reference potential, an adjustment amount of the second clock signal per adjustment changes.

Abstract: To provide a DLL circuit including: a first phase determination circuit that compares phases of rising edges of an external clock and a first internal clock; a second phase determination circuit that compares phases of falling edges of the external clock and the first internal clock; an adjusting unit that adjusts positions of active edges of internal clocks based on determination results; and a control circuit that sets one of adjustment amounts of the second and third internal clocks to a larger value than the other, in response to a fact that adjustment directions of the active edges of the second and third internal clocks are mutually the same. With this arrangement, a duty can be set nearer to 50% while performing phase adjustment. Accordingly, the time required to lock the DLL circuit can be shortened.

Abstract: A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V2 from a first voltage V1; and a control circuit that generates the current control signal OVDR, makes a current that is flowed by the current mirror increase by a first transition of the current control signal OVDR, and makes the current that is flowed by the current mirror decrease by a second transition of the current control signal OVDR. The control circuit includes a slew-rate processing unit that makes a second slew rate of the current control signal OVDR related to the second transition be smaller than a first slew rate of the current control signal OVDR related to the first transition.

Abstract: A semiconductor device includes a delay circuit supplied with a first clock signal and a first phase determination signal and producing a second clock signal, the delay circuit controlling the second clock signal such that a delay in phase of the second clock signal to the first clock signal is increased when the first phase determination signal takes a first logic level and decreased when the first phase determination signal takes a second logic level, and a phase determining circuit supplied with the first clock signal and a third clock signal, which is produced in response to the second clock signal, and producing a second phase determination signal in response to a difference in phase between the first clock signal and the third clock signal.

Abstract: A semiconductor device includes a delay circuit supplied with a first clock signal and a first phase determination signal and producing a second clock signal, the delay circuit controlling the second clock signal such that a delay in phase of the second clock signal to the first clock signal is increased when the first phase determination signal takes a first logic level and decreased when the first phase determination signal takes a second logic level, and a phase determining circuit supplied with the first clock signal and a third clock signal, which is produced in response to the second clock signal, and producing a second phase determination signal in response to a difference in phase between the first clock signal and the third clock signal.

Abstract: A semiconductor device with a clock control circuit that outputs an internal clock signal configured by delaying external clock signals based on at least a feedback clock signal; a plurality of output buffers that output data in synchronization with the internal clock signal; an output replica that is a replica of the output buffers and that generates the feedback clock signal in synchronization with the internal clock signal and supplies the feedback clock signal to the clock control circuit; and a clock tree that receives the internal clock signal from the clock control circuit and transmits the internal clock signal to the plurality of output buffers and the output replica such that signal line are substantially equal to one another.

Abstract: A semiconductor device includes: an input node supplied with an input signal; an output node provided correspondingly to the input node; first and second input circuits coupled in parallel to each other between the input and output nodes; and a control circuit configured to control the first and second input circuits such that one of the first and second input circuits is switched over from an active state to an inactive state and the other of the first and second input circuits is switched over from an inactive state to an active state during the one of the first and second input circuits being still in the active state.

Abstract: A semiconductor device includes a regulator including an operational amplifier configured of a current mirror and generating the second voltage V2 from a first voltage V1; and a control circuit that generates the current control signal OVDR, makes a current that is flowed by the current mirror increase by a first transition of the current control signal OVDR, and makes the current that is flowed by the current mirror decrease by a second transition of the current control signal OVDR. The control circuit includes a slew-rate processing unit that makes a second slew rate of the current control signal OVDR related to the second transition be smaller than a first slew rate of the current control signal OVDR related to the first transition.

Abstract: A clock control circuit includes a phase determination circuit that generates a first phase determination signal based on a phase of an external clock signal, a counter circuit that updates a count value based on a second phase determination signal for each sampling period, a delay line that generates an internal clock signal by delaying the external clock signal based on the count value, and an invalidation circuit that generates the second phase determination signal which is obtained by invalidating a change of the first phase determination signal within a same sampling period in response to a fact that the first phase determination circuit indicates a predetermined logical level.

Abstract: To include a first level shift circuit that converts a first internal clock signal having an amplitude value of a first voltage into a second internal clock signal having an amplitude value of a second voltage, a second level shift circuit that converts a first internal data signal having the amplitude value of the first voltage into a second internal data signal having the amplitude value of the second voltage, a clock dividing circuit that generates third and fourth internal clock signals, which are complementary signals, based on the second internal clock signal, and an output circuit that outputs external data signals continuously from a data output terminal in synchronization with the third and fourth internal clock signals based on the second internal data signal. According to the present invention, because a level shift of a signal is performed before it is input to the output circuit, there occurs no skew in output data.

Abstract: To include a phase determining circuit that generates a first phase determination signal, a sampling circuit that samples the first phase determination signal and generates a second phase determination signal based on the sampled first phase determination signal, and a clock generating unit that generates an internal clock signal based on the second phase determination signal. The sampling circuit includes a continuity determining circuit that fixes the second phase determination signal when a logic level of the first phase determination signal changes within a sampling cycle, an initial operation circuit that fixes the second phase determination signal at a high level until when a third phase determination signal indicates a high level, and a disabling circuit that disables an operation of the continuity determining circuit after the third phase determination signal indicates a high level.

Abstract: A semiconductor device includes a first duty determining circuit (20) and a second duty determining circuit (30). The first duty determining circuit (20) determines a duty correction condition for an input signal in a first predetermined cycle longer than a cycle of the input signal to obtain a first determination result and updates the duty correction condition for the input signal on the basis of the first determination result. The second duty determining circuit (30) determines the duty correction condition for the input signal in a second predetermined cycle shorter than first predetermined cycle to obtain a second determination result and updates the duty correction condition for the input signal only when the second determination result is fixed during a predetermined period.