Patents by Inventor Kazuya Ishiwata

Kazuya Ishiwata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080001516
    Abstract: To provide an electron source including: a wiring board having: a substrate having a groove on its surface; a conductive wire containing a metal which is arranged along the groove in the groove; and a wiring which is arranged above the wire crossing the wire; and an electron-emitting device which is arranged on the wiring board and is electrically connected to the conductive wire and the wiring; wherein the wire has an oxide layer of the metal contained in the wire on its surface.
    Type: Application
    Filed: June 21, 2007
    Publication date: January 3, 2008
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: MASAFUMI MORIYA, KAZUYA ISHIWATA
  • Patent number: 7285428
    Abstract: In a production method of an electron source wherein a plurality of electron-emitting devices are connected by and driven by matrix wirings, the upper wiring of the matrix wiring is partially removed at a short circuit region at a cross portion between the matrix wirings, thereby removing the short circuit and effectively repairing an electrical connecting relation of the matrix wirings.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: October 23, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata
  • Patent number: 7264842
    Abstract: A manufacturing method for a wiring substrate for a display panel having a plurality of wiring electrodes thereon includes the step of forming wirings in an orthogonal projection area of an image forming member onto the wiring substrate by photolithography using a photo paste. In addition, wires are formed in an area where the frame member is disposed by pattern printing using paste ink for printing.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: September 4, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Shinsaku Kubo
  • Patent number: 7211943
    Abstract: A covering layer for insulating between column wirings and device electrodes is formed in a region including each cross point of the column wirings and row wirings and under the column wirings. Thus, when an electron source plate in which a large number of electron-emitting devices are wired in passive matrix is formed, a defect resulting from an interaction between the device electrodes and the column wirings at the time of wiring formation is reduced to improve insulation reliability. Therefore, a high quality image is obtained by a large size and higher density pixel arrangement in an image-forming apparatus using the electron source plate.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: May 1, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Shinsaku Kubo
  • Publication number: 20060194156
    Abstract: A method for forming patterned insulating elements on a substrate includes a plurality of exposure steps of exposing a photosensitive paste provided on the substrate through at least one mask having a predetermined pattern; a developing step of developing the exposed photosensitive paste to form a precursor pattern; and a firing step of firing the precursor pattern to form the patterned insulating elements. This method is applied to a method for forming an electron source and a method for forming an image display device including the electron source.
    Type: Application
    Filed: May 2, 2006
    Publication date: August 31, 2006
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Yoshimi Uda, Shinsaku Kubo
  • Patent number: 7095168
    Abstract: An electron source forming substrate comprises an insulating material film provided on a substrate surface, where an electron-emitting device is arranged. The insulating material film contains a metallic oxide and has a vacancy, so that the vacancy suppresses diffusion of Na from a substrate thereunder, thereby electron-emitting characteristic is maintained stable without adverse effect due to Na even after long time operation.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: August 22, 2006
    Assignee: Canon KAbushiki Kaisha
    Inventors: Tadayasu Meguro, Kazuya Ishiwata, Shuji Yamada, Fumikazu Kobayashi
  • Patent number: 7052825
    Abstract: A substrate includes fine lines. The fine lines are obtained according to a fine-line forming process, which includes a process of projecting light from above the substrate onto predetermined regions on a photosensitive material provided on the substrate and a developing process after the light projection process. A narrow-width portion is provided at an end portion of each of the fine lines in a longitudinal direction of the fine line. The width of the narrow-width portion is smaller than the width of a portion adjacent to the narrow-width portion.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: May 30, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Patent number: 7052823
    Abstract: A method of manufacturing an electroconductive film subject to edge curl due to volume contraction after baking includes sequentially repeating a film-forming step of forming a film containing a photosensitive material and an electroconductive material therein and an exposure step of irradiating a light onto a desired region of the film for a plurality of times to laminate the films. The latent images of the respective layers are integrated. The resulting latent image is developed by removing a non-latent image region of the laminate film after the laminate film is formed. Finally, the developed image is baked. The sequential repetition of the film-forming step and the exposure step act to counteract edge curl formed by volume contraction after baking.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: May 30, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Patent number: 7015637
    Abstract: As a substrate having a fine line and capable of suppressing crack generation in the substrate and peeling of the fine line, the invention discloses a configuration in which plural recesses are arranged on the fine line, and particularly a configuration in which the interval of the plural recesses does not exceed 200 ?m. There is also disclosed a configuration in which the plural recesses are arranged along a direction crossing the longitudinal direction of the fine line.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: March 21, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Patent number: 6962770
    Abstract: In a method of manufacturing an electroconductive film, a developing process is implemented on a photosensitive paste layer (12) having a height of about 13 ?m in a state where exposure is repeated twice in FIG. 1D, and thereafter, a baking process is completed to form a wiring pattern (20). As a result, the curling of an edge formed in the wiring pattern (20) can be remarkably reduced.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: November 8, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Publication number: 20050200267
    Abstract: As a substrate having a fine line and capable of suppressing crack generation in the substrate and peeling of the fine line, the invention discloses a configuration in which plural recesses are arranged on the fine line, and particularly a configuration in which the interval of the plural recesses does not exceed 200 ?m. There is also disclosed a configuration in which the plural recesses are arranged along a direction crossing the longitudinal direction of the fine line.
    Type: Application
    Filed: May 12, 2005
    Publication date: September 15, 2005
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Publication number: 20050189867
    Abstract: A covering layer for insulating between column wirings and device electrodes is formed in a region including each cross point of the column wirings and row wirings and under the column wirings. Thus, when an electron source plate in which a large number of electron-emitting devices are wired in passive matrix is formed, a defect resulting from an interaction between the device electrodes and the column wirings at the time of wiring formation is reduced to improve insulation reliability. Therefore, a high quality image is obtained by a large size and higher density pixel arrangement in an image-forming apparatus using the electron source plate.
    Type: Application
    Filed: May 2, 2005
    Publication date: September 1, 2005
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Shinsaku Kubo
  • Publication number: 20050170536
    Abstract: In a production method of an electron source wherein a plurality of electron-emitting devices are connected by and driven by matrix wirings, the upper wiring of the matrix wiring is partially removed at a short circuit region at a cross portion between the matrix wirings, thereby removing the short circuit and effectively repairing an electrical connecting relation of the matrix wirings.
    Type: Application
    Filed: January 21, 2005
    Publication date: August 4, 2005
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yoshimi Uda, Kazuya Ishiwata
  • Publication number: 20050148269
    Abstract: In a method of manufacturing an electron-emitting device, an electroconductive film formed on a substrate is subjected to a clean processing to remove a foreign matter from the electroconductive film, and thereafter, energization is conducted on the electroconductive film, to form an electron-emitting region. Accordingly, there is provided an electron-emitting device which avoids a formation defect of the electron-emitting region due to the existence of the foreign matter and which has satisfactory characteristics without fluctuation.
    Type: Application
    Filed: December 21, 2004
    Publication date: July 7, 2005
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yoshimi Uda, Yoshihiro Yanagisawa, Kazuya Ishiwata
  • Patent number: 6903504
    Abstract: A covering layer for insulating between column wirings and device electrodes is formed in a region including each cross point of the column wirings and row wirings and under the column wirings. Thus, when an electron source plate in which a large number of electron-emitting devices are wired in passive matrix is formed, a defect resulting from an interaction between the device electrodes and the column wirings at the time of wiring formation is reduced to improve insulation reliability. Therefore, a high quality image is obtained by a large size and higher density pixel arrangement in an image-forming apparatus using the electron source plate.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: June 7, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Shinsaku Kubo
  • Patent number: 6902455
    Abstract: There is provided a method of manufacturing a member pattern having on a substrate, a patterned first belt-shaped member and a plurality of second belt-shaped members that are patterned over from the first belt-shaped member to the substrate, the method including: forming the first belt-shaped member by a printing method; and forming the second belt-shaped members by a process involving exposure and development using a photosensitive material.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: June 7, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshihiro Yanagisawa, Kazuya Ishiwata, Hiroaki Toshima
  • Publication number: 20050101051
    Abstract: In a method of manufacturing an electroconductive film, a developing process is implemented on a photosensitive paste layer (12) having a height of about 13 ?m in a state where exposure is repeated twice in FIG. 1D, and thereafter, a baking process is completed to form a wiring pattern (20). As a result, the curling of an edge formed in the wiring pattern (20) can be remarkably reduced.
    Type: Application
    Filed: July 23, 2003
    Publication date: May 12, 2005
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Publication number: 20050062391
    Abstract: In an electron source having an electron emitting member, the electron emitting member is connected to a first or second conductive member by a third conductive member which is connected to the first or second conductive member through an aperture forming in an insulating member, and such aperture has such a shape as to become narrower from an end of the third conductive member toward the other end. Such configuration avoids that the third conductive member is damaged in the connecting portion with the first or second conductive member by the thermal stress therein.
    Type: Application
    Filed: October 7, 2004
    Publication date: March 24, 2005
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hiroaki Toshima, Kazuya Ishiwata, Yoshimi Uda
  • Patent number: 6866989
    Abstract: A method for forming patterned insulating elements on a substrate includes a plurality of exposure steps of exposing a photosensitive paste provided on the substrate through at least one mask having a predetermined pattern; a developing step of developing the exposed photosensitive paste to form a precursor pattern; and a firing step of firing the precursor pattern to form the patterned insulating elements. This method is applied to a method for forming an electron source and a method for forming an image display device including the electron source.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: March 15, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Yoshimi Uda, Shinsaku Kubo
  • Patent number: 6853117
    Abstract: In an electron source having an electron emitting member, the electron emitting member is connected to a first or second conductive member by a third conductive member which is connected to the first or second conductive member through an aperture forming in an insulating member, and such aperture has such a shape as to become narrower from an end of the third conductive member toward the other end. Such configuration avoids that the third conductive member is damaged in the connecting portion with the first or second conductive member by the thermal stress therein.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: February 8, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroaki Toshima, Kazuya Ishiwata, Yoshimi Uda