Patents by Inventor Kazuya Ishiwata

Kazuya Ishiwata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050019707
    Abstract: A method for forming patterned insulating elements on a substrate includes a plurality of exposure steps of exposing a photosensitive paste provided on the substrate through at least one mask having a predetermined pattern; a developing step of developing the exposed photosensitive paste to form a precursor pattern; and a firing step of firing the precursor pattern to form the patterned insulating elements. This method is applied to a method for forming an electron source and a method for forming an image display device including the electron source.
    Type: Application
    Filed: August 9, 2004
    Publication date: January 27, 2005
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Yoshimi Uda, Shinsaku Kubo
  • Publication number: 20040259038
    Abstract: A manufacturing method for a wiring substrate for a display panel having a plurality of wiring electrodes thereon includes the step of forming wirings in an orthogonal projection area of an image forming member onto the wiring substrate by photolithography using a photo paste. In addition, wires are formed in an area where the frame member is disposed by pattern printing using paste ink for printing.
    Type: Application
    Filed: July 9, 2004
    Publication date: December 23, 2004
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Shinsaku Kubo
  • Patent number: 6815884
    Abstract: An electron source forming substrate wherein an insulating material film is disposed on the surface of the substrate at which surface an electron-emitting device is arranged. The insulating material film contains a plurality of metallic oxide particles having an average particle size within the range of 6 nm to 60 nm as expressed in a median value, and suppresses undesirable diffusion of Na from the substrate, thereby makes stable an electron-emitting characteristics, without an adverse effect due to the Na diffusion, even elapsing longer time.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: November 9, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shuji Yamada, Kazuya Ishiwata, Tadayasu Meguro
  • Patent number: 6803707
    Abstract: Disclosed is an electron source forming substrate provided with an insulating material layer provided on the surface of a substrate, at which surface an electron-emitting device is disposed, wherein the insulating material layer has a plurality of partially exposed metal oxide particles on its surface. Also disclosed are an electron source including a substrate and an electron-emitting device arranged on the substrate, wherein the substrate is an electron source forming substrate as described above, and an image display apparatus including an envelope, an electron-emitting device arranged in the envelope, and an image display member adapted to display images through application of electrons from the electron-emitting device, wherein a substrate on which the electron-emitting device is arranged is an electron source forming substrate as described above.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: October 12, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuya Ishiwata, Shuji Yamada, Tadayasu Meguro
  • Patent number: 6787984
    Abstract: A wiring substrate for a display panel having a plurality of wiring electrodes thereon includes an airtight container formed by disposing an opposing substrate through a frame member on the surface of the substrate having the wiring electrodes. The airtight container has an image forming member therein, in which an average angle between a cross section of the wirings and the wiring substrate in an orthogonal projection area of the image forming member onto the wiring substrate is obtuse, while an average angle between a cross section of the wirings and the wiring substrate in an area where the frame member is disposed is acute.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: September 7, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Shinsaku Kubo
  • Publication number: 20040161703
    Abstract: A substrate includes fine lines. The fine lines are obtained according to a fine-line forming process, which includes a process of projecting light from above the substrate onto predetermined regions on a photosensitive material provided on the substrate and a developing process after the light projection process. A narrow-width portion is provided at an end portion of each of the fine lines in a longitudinal direction of the fine line. The width of the narrow-width portion is smaller than the width of a portion adjacent to the narrow-width portion.
    Type: Application
    Filed: February 20, 2004
    Publication date: August 19, 2004
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Patent number: 6758712
    Abstract: The wirings on an electron source substrate are formed to intersect with each other in a matrix so as to address the electron emission devices on the substrate. First and second wirings intersect with each other on a crossing point. As such a crossing point, an insulating layer is placed between the first and second wirings. To ensure insulation, a plurality of insulating layers are laminated. According to the present invention, a wiring pattern is provided on the substrate with a conductive paste and baking the wiring pattern of the conductive paste to form the first wiring. Subsequently part of the first wiring is coated at the crossing point with an insulating paste and baking the insulating paste to form a first insulating layer. The coating thickness of the insulating layer formed adjacent to sidewalls of the crossing point is substanially equal to the height of the first wiring.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: July 6, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shinsaku Kubo, Kazuya Ishiwata, Yoshimi Uda, Yasuyuki Watanabe, Hiroaki Toshima
  • Patent number: 6720120
    Abstract: A substrate includes fine lines. The fine lines are obtained according to a fine-line forming process, which includes a process of projecting light from above the substrate onto predetermined regions on a photosensitive material provided on the substrate and a developing process after the light projection process. A narrow-width portion is provided at an end portion of each of the fine lines in a longitudinal direction of the fine line. The width of the narrow-width portion is smaller than the width of a portion adjacent to the narrow-width portion.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: April 13, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Publication number: 20040027054
    Abstract: As a substrate having a fine line and capable of suppressing crack generation in the substrate and peeling of the fine line, the invention discloses a configuration in which plural recesses are arranged on the fine line, and particularly a configuration in which the interval of the plural recesses does not exceed 200 &mgr;m. There is also disclosed a configuration in which the plural recesses are arranged along a direction crossing the longitudinal direction of the fine line.
    Type: Application
    Filed: August 11, 2003
    Publication date: February 12, 2004
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Patent number: 6653232
    Abstract: A method of manufacturing wiring includes a step of forming a conductive layer pattern through a developing step after performing film formation and exposure step using photosensitive paste that contains a photosensitive material and a conductive material, a step of forming an insulating layer pattern through a developing step after performing film formation and exposure step using photosensitive paste that contains a photosensitive material and an insulating material, and a baking step for baking the conductive layer pattern and the insulating layer pattern. Thus, a wiring pattern can be formed with high precision by reducing an edge curl.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: November 25, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata
  • Patent number: 6621207
    Abstract: As a substrate having a fine line and capable of suppressing crack generation in the substrate and peeling of the fine line, the invention discloses a configuration in which plural recesses are arranged on the fine line, and particularly a configuration in which the interval of the plural recesses does not exceed 200 &mgr;m. There is also disclosed a configuration in which the plural recesses are arranged along a direction crossing the longitudinal direction of the fine line.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: September 16, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Publication number: 20030141523
    Abstract: A covering layer for insulating between column wirings and device electrodes is formed in a region including each cross point of the column wirings and row wirings and under the column wirings. Thus, when an electron source plate in which a large number of electron-emitting devices are wired in passive matrix is formed, a defect resulting from an interaction between the device electrodes and the column wirings at the time of wiring formation is reduced to improve insulation reliability. Therefore, a high quality image is obtained by a large size and higher density pixel arrangement in an image-forming apparatus using the electron source plate.
    Type: Application
    Filed: January 22, 2003
    Publication date: July 31, 2003
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Shinsaku Kubo
  • Publication number: 20030060114
    Abstract: There is provided a method of manufacturing a member pattern having on a substrate, a patterned first belt-shaped member and a plurality of second belt-shaped members that are patterned over from the first belt-shaped member to the substrate, the method including: forming the first belt-shaped member by a printing method; and forming the second belt-shaped members by a process involving exposure and development using a photosensitive material.
    Type: Application
    Filed: September 12, 2002
    Publication date: March 27, 2003
    Inventors: Yoshihiro Yanagisawa, Kazuya Ishiwata, Hiroaki Toshima
  • Publication number: 20030049572
    Abstract: A method for forming patterned insulating elements on a substrate includes a plurality of exposure steps of exposing a photosensitive paste provided on the substrate through at least one mask having a predetermined pattern; a developing step of developing the exposed photosensitive paste to form a precursor pattern; and a firing step of firing the precursor pattern to form the patterned insulating elements. This method is applied to a method for forming an electron source and a method for forming an image display device including the electron source.
    Type: Application
    Filed: September 6, 2002
    Publication date: March 13, 2003
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Yoshimi Uda, Shinsaku Kubo
  • Publication number: 20030038585
    Abstract: To provide a wiring substrate which solves a problem in that the airtightness is decreased (a leak path is formed) at an outer periphery of a display area where a panel is seal-bonded, which is a wiring substrate for a display panel having a plurality of wiring electrodes thereon, with an airtight container being formed by disposing an opposing substrate through a frame member on the surface of the substrate having the wiring electrodes, and the airtight container having an image forming member therein, in which average angle between a cross section of the wirings and the wiring substrate in an orthogonal projection area of the image forming member onto the wiring substrate is obtuse, while average angle between a cross section of the wirings and the wiring substrate in an area where the frame member is disposed is acute.
    Type: Application
    Filed: August 26, 2002
    Publication date: February 27, 2003
    Applicant: Cannon Kabushiki Kaisha
    Inventors: Yasuyuki Watanabe, Kazuya Ishiwata, Shinsaku Kubo
  • Publication number: 20030030357
    Abstract: In an electron source having an electron emitting member, the electron emitting member is connected to a first or second conductive member by a third conductive member which is connected to the first or second conductive member through an aperture forming in an insulating member, and such aperture has such a shape as to become narrower from an end of the third conductive member toward the other end. Such configuration avoids that the third conductive member is damaged in the connecting portion with the first or second conductive member by the thermal stress therein.
    Type: Application
    Filed: July 31, 2002
    Publication date: February 13, 2003
    Inventors: Hiroaki Toshima, Kazuya Ishiwata, Yoshimi Uda
  • Publication number: 20030027417
    Abstract: A method of manufacturing wiring includes a step of forming a conductive layer pattern through a developing step after performing film formation and exposure step using photosensitive paste that contains a photosensitive material and a conductive material, a step of forming an insulating layer pattern through a developing step after performing film formation and exposure step using photosensitive paste that contains a photosensitive material and an insulating material, and a baking step for baking the conductive layer pattern and the insulating layer pattern. Thus, a wiring pattern can be formed with high precision by reducing an edge curl.
    Type: Application
    Filed: July 31, 2002
    Publication date: February 6, 2003
    Inventors: Yoshimi Uda, Kazuya Ishiwata
  • Publication number: 20020100913
    Abstract: As a substrate having a fine line and capable of suppressing crack generation in the substrate and peeling of the fine line, the invention discloses a configuration in which plural recesses are arranged on the fine line, and particularly a configuration in which the interval of the plural recesses does not exceed 200 &mgr;m. There is also disclosed a configuration in which the plural recesses are arranged along a direction crossing the longitudinal direction of the fine line.
    Type: Application
    Filed: December 14, 2001
    Publication date: August 1, 2002
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Publication number: 20020095785
    Abstract: The wirings on an electron source substrate are formed to intersect with each other in a matrix so as to address the electron emission devices on the substrate. First and second wirings intersect with each other on a crossing point. As such a crossing point, an insulating layer is placed between the first and second wirings. To ensure insulation, a plurality of insulating layers are laminated. According to the present invention, a wiring pattern is provided on the substrate with a conductive paste and baking the wiring pattern of the conductive paste to form the first wiring. Subsequently part of the first wiring is coated at the crossing point with an insulating paste and baking the insulating paste to form a first insulating layer. The coating thickness of the insulating layer formed adjacent to sidewalls of the crossing point is substanially equal to the height of the first wiring.
    Type: Application
    Filed: December 11, 2001
    Publication date: July 25, 2002
    Inventors: Shinsaku Kubo, Kazuya Ishiwata, Yoshimi Uda, Yasuyuki Watanabe, Hiroaki Toshima
  • Publication number: 20020074557
    Abstract: A substrate includes fine lines. The fine lines are obtained according to a fine-line forming process, which includes a process of projecting light from above the substrate onto predetermined regions on a photosensitive material provided on the substrate and a developing process after the light projection process. A narrow-width portion is provided at an end portion of each of the fine lines in a longitudinal direction of the fine line. The width of the narrow-width portion is smaller than the width of a portion adjacent to the narrow-width portion.
    Type: Application
    Filed: December 6, 2001
    Publication date: June 20, 2002
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe