Abstract: A deep power down control circuit includes a deep power down switch unit to separate an external power voltage line from a selected one of a plurality of internal power voltage lines according to a deep power down signal, a deep power down discharge unit for connecting the plurality of internal power voltage lines to a ground voltage line and to discharge them to a ground voltage level according to the deep power down signal. The deep power down control circuit also includes a deep power down signal generating unit control according to a bank active detect signal and a burst end command, to output the deep power down signal by using a clock enable signal. The deep power down control circuit connects the plurality of internal power voltage lines to the ground voltage line, and thus prevents floating to remove the possibility of inversion of the power voltage or generation of the latch-up.

Abstract: Disclosed is a semiconductor memory device which is capable of reducing noise during an operation thereof by individually supplying clamping voltages to respective banks. The semiconductor memory device includes: a plurality of banks; a plurality of clamping voltage supply units corresponding to the plurality of banks, for supplying clamping voltages to the corresponding banks, in which the clamping voltages are obtained by clamping an external power supply voltage to a predetermined level; and a clamping voltage control units for controlling the plurality of clamping voltage supply units to allow the corresponding clamping voltages to be supplied to selected banks while the selected banks are activated.

Abstract: An internal power voltage generator for achieving stable operation of a semiconductor device by selectively connecting an external power voltage terminal to a supply line of an internal power voltage in an operation power potential range of the semiconductor device, and generating a predetermined reference voltage in a reference voltage generator in accordance with the internal power voltage after a predetermined potential.

Abstract: A deep power down control circuit includes a deep power down switch unit to separate an external power voltage line from a selected one of a plurality of internal power voltage lines according to a deep power down signal, a deep power down discharge unit for connecting the plurality of internal power voltage lines to a ground voltage line and to discharge them to a ground voltage level according to the deep power down signal. The deep power down control circuit also includes a deep power down signal generating unit control according to a bank active detect signal and a burst end command, to output the deep power down signal by using a clock enable signal. The deep power down control circuit connects the plurality of internal power voltage lines to the ground voltage line, and thus prevents floating to remove the possibility of inversion of the power voltage or generation of the latch-up.

Abstract: A semiconductor memory test device is capable of reducing the test time and increasing test reliability by applying an effective stress in a burn-in level or a wafer level. The semiconductor memory test device controls a sense amplifier using an additional sense amplifier driving signal when a 2rb pattern stress is applied. Therefore, the semiconductor memory test device applies a uniform stress by applying the constant supply voltage to a cell corresponding to the entire wordlines.

Abstract: A power-up signal generator for a semiconductor memory device that uses the deep power down power-up signal for a semiconductor element, which should be in a standby state in the deep power down entry, and the power-up signal for an initialization of another semiconductor elements in a DRAM device that operates after an internal power supply voltage is generated is disclosed. The generator also uses the power-up signal, which is disabled in the deep power down entry and enabled in a deep power down exit by the internal power supply voltage.

Abstract: An internal power voltage generator for achieving stable operation of a semiconductor device by selectively connecting an external power voltage terminal to a supply line of an internal power voltage in an operation power potential range of the semiconductor device, and generating a predetermined reference voltage in a reference voltage generator in accordance with the internal power voltage after a predetermined potential.

Abstract: A voltage generator is disclosed which has a charge pump unit including a pump transistor for performing a charge pumping operation by a pump control signal from a ring oscillator and a precharge transistor for performing a charge precharge operation by a precharge control signal from the ring oscillator. The voltage generator additionally has a controller which provides a new back-bias control signal by combining the pump control signal from the ring oscillator with the precharge control signal from the ring oscillator and controls a threshold voltage of the precharge transistor with the back-bias control signal.