Patents by Inventor Keiichi Sasaki

Keiichi Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130316523
    Abstract: A method of manufacturing a semiconductor device having a twin well structure is provided. The method includes ion-implanting of a first conductivity type impurity in a first region and a second region of a semiconductor substrate, the first and second regions being located adjacent to each other; forming a first resist pattern to cover the first region of the semiconductor substrate and to expose the second region of the semiconductor substrate; ion-implanting of a second conductivity type impurity at a higher concentration compared to the first conductivity type impurity in the second region of the semiconductor substrate, with the first resist pattern being used as a mask; and thermal-diffusing the first conductivity type of impurity and the second conductivity type of impurity.
    Type: Application
    Filed: May 8, 2013
    Publication date: November 28, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Nobuyuki Suzuki, Tomohiro Migita, Satoshi Suzuki, Masanobu Ohmura, Takatoshi Nakahara, Keiichi Sasaki
  • Patent number: 8409452
    Abstract: A through-hole forming method includes steps of forming a first impurity region (102a) around a region where a through-hole is to be formed in the first surface of a silicon substrate (101), the first impurity region (102) being higher in impurity concentration than the silicon substrate (101), forming a second impurity region (102b) at a position adjacent to the first impurity region (102a) in the depth direction of the silicon substrate (101), the second impurity region (102b) being higher in impurity concentration than the first impurity region (102a), forming an etch stop layer (103) on the first surface, forming an etch mask layer (104) having an opening on the second surface of the silicon substrate (101) opposite to the first surface, and etching the silicon substrate (101) until at least the etch stop layer (103) is exposed via the opening.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: April 2, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keiichi Sasaki, Yukihiro Hayakawa
  • Publication number: 20120257855
    Abstract: PROBLEM An object of the present invention is to easily and inexpensively manufacture an array-type photo module and, in addition, coexist high-density array and low crosstalk. SOLUTION The present invention provides an array-type photo module M including a filter 31, which, in each channel, transmits therethrough a portion of emitting light from an incident optical fiber 11 on the opposite side of a gradient-index lens array 2 and reflects another portion of the emitting light from the incident optical fiber 11 toward the gradient-index lens array 2, and a light-shielding member 32 (33) which is arranged on the opposite side of the gradient-index lens array 2 of the filter 31 so as to be spaced from the filter 31 and, in each channel, has an opening 34 (35) passing therethrough transmitted light from the filter 31 on the opposite side of the filter 31.
    Type: Application
    Filed: March 1, 2012
    Publication date: October 11, 2012
    Inventors: Yuto Yamashita, Keiichi Sasaki, Etsuo Ogino, Yasuaki Tamura, Yuji Akahori, Yuichi Suzuki
  • Patent number: 8283755
    Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: October 9, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuo Hayasaka, Katsuya Okumura, Keiichi Sasaki, Mie Matsuo
  • Patent number: 8174093
    Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: May 8, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuo Hayasaka, Katsuya Okumura, Keiichi Sasaki, Mie Matsuo
  • Patent number: 8157357
    Abstract: The present invention provides a higher density, higher resolution, higher durability and lower cost circuit substrate. In a circuit substrate in which a circuit including: a plurality of heat generating elements in which a pair of electrodes opposing each other to form a predetermined gap is provided on a resistor 16 and a portion where a resistor layer is positioned between the electrodes is taken as a resistor portion; and first and second wiring layers 12 and 15 for energizing the pair of electrodes of each heat generating element; is mounted on a substrate 10, the substrate is formed of Si, the first wiring layer is formed of a metal material containing at least Si, the first wiring layer is electrically connected to the substrate, the second wiring layer is provided on the first wiring layer through a metal film 14 for preventing Si from diffusing and a resistor is provided over the second wiring layer.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: April 17, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Keiichi Sasaki
  • Publication number: 20110215443
    Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.
    Type: Application
    Filed: May 13, 2011
    Publication date: September 8, 2011
    Inventors: Nobuo Hayasaka, Katsuya Okumura, Keiichi Sasaki, Mie Matsuo
  • Publication number: 20110101522
    Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.
    Type: Application
    Filed: October 26, 2010
    Publication date: May 5, 2011
    Inventors: Nobuo Hayasaka, Katsuya Okumura, Keiichi Sasaki, Mie Matsuo
  • Patent number: 7829975
    Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: November 9, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuo Hayasaka, Katsuya Okumura, Keiichi Sasaki, Mie Matsuo
  • Patent number: 7711217
    Abstract: An active sensor 10 is positioned on an outside of a pipe 60 so as to detect a thickness of the pipe. The active sensor comprises: an oscillator 15 capable of inputting oscillatory waves into the pipe and sweeping a frequency of the oscillatory waves within a desired range; and an optical fiber sensor mounted on the pipe, the optical fiber sensor detecting the oscillatory waves generated in the pipe.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: May 4, 2010
    Assignees: Kabushiki Kaisha Toshiba, Lazoc Incorporated
    Inventors: Masashi Takahashi, Keiichi Sasaki, Nobuo Yamaga, Norio Ahiko, Koichi Yoshimura, Masanobu Ohi, Yoshio Mochida, Yuuichi Machijima, Takehiro Shirai
  • Publication number: 20090267989
    Abstract: The present invention provides a higher density, higher resolution, higher durability and lower cost circuit substrate. In a circuit substrate in which a circuit including: a plurality of heat generating elements in which a pair of electrodes opposing each other to form a predetermined gap is provided on a resistor 16 and a portion where a resistor layer is positioned between the electrodes is taken as a resistor portion; and first and second wiring layers 12 and 15 for energizing the pair of electrodes of each heat generating element; is mounted on a substrate 10, the substrate is formed of Si, the first wiring layer is formed of a metal material containing at least Si, the first wiring layer is electrically connected to the substrate, the second wiring layer is provided on the first wiring layer through a metal film 14 for preventing Si from diffusing and a resistor is provided over the second wiring layer.
    Type: Application
    Filed: April 24, 2009
    Publication date: October 29, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Keiichi Sasaki
  • Publication number: 20090073228
    Abstract: A through-hole forming method includes steps of forming a first impurity region (102a) around a region where a through-hole is to be formed in the first surface of a silicon substrate (101), the first impurity region (102) being higher in impurity concentration than the silicon substrate (101), forming a second impurity region (102b) at a position adjacent to the first impurity region (102a) in the depth direction of the silicon substrate (101), the second impurity region (102b) being higher in impurity concentration than the first impurity region (102a), forming an etch stop layer (103) on the first surface, forming an etch mask layer (104) having an opening on the second surface of the silicon substrate (101) opposite to the first surface, and etching the silicon substrate (101) until at least the etch stop layer (103) is exposed via the opening.
    Type: Application
    Filed: August 25, 2008
    Publication date: March 19, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Keiichi Sasaki, Yukihiro Hayakawa
  • Publication number: 20080260324
    Abstract: An active sensor 10 is positioned on an outside of a pipe 60 so as to detect a thickness of the pipe. The active sensor comprises: an oscillator 15 capable of inputting oscillatory waves into the pipe and sweeping a frequency of the oscillatory waves within a desired range; and an optical fiber sensor mounted on the pipe, the optical fiber sensor detecting the oscillatory waves generated in the pipe.
    Type: Application
    Filed: April 11, 2008
    Publication date: October 23, 2008
    Applicants: KABUSHIKI KAISHA TOSHIBA, LAZOC INCORPORATED
    Inventors: Masashi TAKAHASHI, Keiichi Sasaki, Nobuo Yamaga, Norio Ahiko, Koichi Yoshimura, Masanobu Ooi, Yoshio Mochida, Yuuichi Machijima, Takehiro Shirai
  • Publication number: 20080237888
    Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.
    Type: Application
    Filed: October 31, 2007
    Publication date: October 2, 2008
    Inventors: Nobuo Hayasaka, Katsuya Okumura, Keiichi Sasaki, Mie Matsuo
  • Patent number: 7335517
    Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: February 26, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuo Hayasaka, Katsuya Okumura, Keiichi Sasaki, Mie Matsuo
  • Patent number: 7309657
    Abstract: Provided is a method for manufacturing a circuit board including an electrode wiring formed above a surface portion of a substrate, and a plurality of electrothermal converting elements which have a heating resistor film for generating thermal energy formed above the electrode wiring. The method includes: forming an electrode wiring layer for forming the electrode wiring, forming the heating resistor film; and collectively etching the electrode wiring layer and the heating resistor film to thereby form the electrode wiring. With the method according to the present invention, the circuit board can be manufactured with a higher density, higher endurance, and lower power consumption recording head to provide high resolution images.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: December 18, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masato Kamiichi, Keiichi Sasaki
  • Patent number: 7270398
    Abstract: A circuit board for a liquid discharging apparatus in which coating performance of a protective layer and a cavitation resistive film on a heat generating element is excellent and durability is excellent and a manufacturing method of such a circuit board are provided. A surface portion of a wiring material layer is processed so that an etching speed of the surface portion is made higher than that of the material forming the wiring material layer. It is desirable to execute a process for forming at least one selected from a fluoride, a chloride, and a nitride of the material forming the wiring material layer into the surface portion of the wiring material layer.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: September 18, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keiichi Sasaki, Masato Kamiichi, Ershad Ali Chowdhury, Yukihiro Hayakawa
  • Patent number: 7244370
    Abstract: In order to provide a circuit substrate with a satisfactory step coverage by the protective layer and the anti-cavitation film in an edge portion of wirings and a liquid discharge head utilizing such circuit substrate, the invention provides a method for producing a circuit substrate provided, on an insulating surface of a substrate, with a plurality of elements each including a resistive layer and a pair of electrodes formed with a predetermined spacing on said resistive layer, including a step of forming an aluminum electrode wiring layer on the resistive layer, a step of isolating the electrode wiring layer by dry etching into each element, and a step of forming the electrode wiring into a tapered cross section with an etching solution containing phosphoric acid, nitric acid and a chelating agent capable of forming a complex with the wiring metal.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: July 17, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keiichi Sasaki, Masato Kamiichi, Yukihiro Hayakawa, Ershad Ali Chowdhury
  • Patent number: 7090339
    Abstract: A method of manufacturing a liquid discharge head, comprising the steps of forming a film of an inorganic material in the form of a liquid flow path pattern on a substrate having liquid discharge elements formed thereon, forming a liquid flow path member on the film of the inorganic material using one of silicon oxide, silicon carbide, and carbon doped silicon oxide (SiOC), forming liquid discharge openings in corresponding portions above the liquid discharge elements, and eluting the film of the inorganic material so as to form a liquid flow path.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: August 15, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventor: Keiichi Sasaki
  • Patent number: 7082384
    Abstract: In an embodiment of this invention, a diagnosis engine refers to a risk assessment DB and anti-risk measure DB, calculates along the time sequence a risk estimate amount in case of failure for each device and a maintenance cost in executing a measure method in advance, and adds the risk estimate amount and maintenance cost along the time sequence to calculate an optimum maintenance period of the device. When a failure has occurred in the device, the diagnosis engine refers to a failure diagnosis DB on the basis of the identification information of the device and the failure mode and analyzes, on the basis of an operation record, a failure which is different from a secular change.
    Type: Grant
    Filed: December 9, 2004
    Date of Patent: July 25, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiichi Sasaki, Akira Sawada, Shigehito Kodera