Patents by Inventor Keiichi Sasaki

Keiichi Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7049223
    Abstract: Form a trench in a major surface of a semiconductor substrate, then bury a paste in the trench. The paste contains solids having a conductive substance and a resin, and solvent for dissolving the resin. The solids content of the paste is not less than 60 vol % and a viscosity ratio thereof is not more than 2.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: May 23, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiichi Sasaki, Manabu Kimura, Yoshimi Hisatsune, Nobuo Hayasaka
  • Patent number: 6978226
    Abstract: A deterioration diagnosis method, wherein the amount of weight loss of a metallic material due to corrosion in atmospheric air for the exposure days is formulated as a function for environmental assessment points which represents a level of a harmfulness of the atmospheric conditions; and the life span of the metallic material is diagnosed based on the corrosion loss calculated from the function.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: December 20, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsumi Kanehira, Yoko Todo, Keiichi Sasaki, Akira Sawada, Kenji Adachi, Kazushige Kimura
  • Patent number: 6933216
    Abstract: After a barrier film is formed on a pad electrode, Ni particles having a diameter of 2 ?m or less are selectively deposited on the barrier film, thereby forming a Ni fine particle film. Then, a bump electrode made of a solder ball is provided on the pad electrode through the Ni fine particle film. Thereafter, the bump electrode is melted by a heat treatment to join the Ni fine particle film to the bump electrode. Thus, a bump electrode structure is finished.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: August 23, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Keiichi Sasaki, Nobuo Hayasaka, Katsuya Okumura, Hirotaka Nishino
  • Publication number: 20050179744
    Abstract: A method of manufacturing a liquid discharge head, comprising the steps of forming a film of an inorganic material in the form of a liquid flow path pattern on a substrate having liquid discharge elements formed thereon, forming a liquid flow path member on the film of the inorganic material using one of silicon oxide, silicon carbide, and carbon doped silicon oxide (SiOC), forming liquid discharge openings in corresponding portions above the liquid discharge elements, and eluting the film of the inorganic material so as to form a liquid flow path.
    Type: Application
    Filed: February 16, 2005
    Publication date: August 18, 2005
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Keiichi Sasaki
  • Patent number: 6930382
    Abstract: A semiconductor device includes a first substrate including an element, a first plug penetrating through the first substrate, made of a conductive material, and electrically connected with the element, a second substrate provided above the first substrate, and electrically connected with the element via the first plug, and a second plug penetrating through the first substrate, made of a non-dielectric material, and being not electrically connected with the second substrate.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: August 16, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kanako Sawada, Keiichi Sasaki
  • Publication number: 20050149570
    Abstract: In an embodiment of this invention, a diagnosis engine refers to a risk assessment DB and anti-risk measure DB, calculates along the time sequence a risk estimate amount in case of failure for each device and a maintenance cost in executing a measure method in advance, and adds the risk estimate amount and maintenance cost along the time sequence to calculate an optimum maintenance period of the device. When a failure has occurred in the device, the diagnosis engine refers to a failure diagnosis DB on the basis of the identification information of the device and the failure mode and analyzes, on the basis of an operation record, a failure which is different from a secular change.
    Type: Application
    Filed: December 9, 2004
    Publication date: July 7, 2005
    Inventors: Keiichi Sasaki, Akira Sawada, Shigehito Kodera
  • Publication number: 20050124164
    Abstract: After a barrier film is formed on a pad electrode, Ni particles having a diameter of 2 ?m or less are selectively deposited on the barrier film, thereby forming a Ni fine particle film. Then, a bump electrode made of a solder ball is provided on the pad electrode through the Ni fine particle film. Thereafter, the bump electrode is melted by a heat treatment to join the Ni fine particle film to the bump electrode. Thus, a bump electrode structure is finished.
    Type: Application
    Filed: January 13, 2005
    Publication date: June 9, 2005
    Inventors: Atsuko Sakata, Keiichi Sasaki, Nobuo Hayasaka, Katsuya Okumura, Hirotaka Nishino
  • Publication number: 20050078152
    Abstract: A circuit board for a liquid discharging apparatus in which coating performance of a protective layer and a cavitation resistive film on a heat generating element is excellent and durability is excellent and a manufacturing method of such a circuit board are provided. A surface portion of a wiring material layer is processed so that an etching speed of the surface portion is made higher than that of the material forming the wiring material layer. It is desirable to execute a process for forming at least one selected from a fluoride, a chloride, and a nitride of the material forming the wiring material layer into the surface portion of the wiring material layer.
    Type: Application
    Filed: October 21, 2004
    Publication date: April 14, 2005
    Applicant: Canon Kabushiki Kaisha
    Inventors: Keiichi Sasaki, Masato Kamiichi, Ershad Chowdhury, Yukihiro Hayakawa
  • Publication number: 20050053774
    Abstract: Provided is a method for manufacturing a circuit board including an electrode wiring formed above a surface portion of a substrate, and a plurality of electrothermal converting elements which have a heating resistor film for generating thermal energy formed above the electrode wiring. The method includes: forming an electrode wiring layer for forming the electrode wiring, forming the heating resistor film; and collectively etching the electrode wiring layer and the heating resistor film to thereby form the electrode wiring. With the method according to the present invention, the circuit board can be manufactured with a higher density, higher endurance, and lower power consumption recording head to provide high resolution images.
    Type: Application
    Filed: August 31, 2004
    Publication date: March 10, 2005
    Applicant: Canon Kabushiki Kaisha
    Inventors: Masato Kamiichi, Keiichi Sasaki
  • Publication number: 20050031996
    Abstract: In order to provide a circuit substrate with a satisfactory step coverage by the protective layer and the anti-cavitation film in an edge portion of wirings and a liquid discharge head utilizing such circuit substrate, the invention provides a method for producing a circuit substrate provided, on an insulating surface of a substrate, with a plurality of elements each including a resistive layer and a pair of electrodes formed with a predetermined spacing on said resistive layer, including a step of forming an aluminum electrode wiring layer on the resistive layer, a step of isolating the electrode wiring layer by dry etching into each element, and a step of forming the electrode wiring into a tapered cross section with an etching solution containing phosphoric acid, nitric acid and a chelating agent capable of forming a complex with the wiring metal.
    Type: Application
    Filed: August 4, 2004
    Publication date: February 10, 2005
    Applicant: Canon Kabushiki Kaisha
    Inventors: Keiichi Sasaki, Masato Kamiichi, Yukihiro Hayakawa, Ershad Chowdhury
  • Publication number: 20050014311
    Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.
    Type: Application
    Filed: July 30, 2004
    Publication date: January 20, 2005
    Inventors: Nobuo Hayasaka, Katsuya Okumura, Keiichi Sasaki, Mie Matsuo
  • Patent number: 6841469
    Abstract: A semiconductor device comprises a first substrate including an element, a first plug penetrating through the first substrate, made of a conductive material, and electrically connected with the element, a second substrate provided above the first substrate, and electrically connected with the element via the first plug, and a second plug penetrating through the first substrate, made of a non-dielectric material, and being not electrically connected with the second substrate.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: January 11, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kanako Sawada, Keiichi Sasaki
  • Patent number: 6838351
    Abstract: A circuit board for a liquid discharging apparatus in which coating performance of a protective layer and a cavitation resistive film on a heat generating element is excellent and durability is excellent and a manufacturing method of such a circuit board are provided. A surface portion of a wiring material layer is processed so that an etching speed of the surface portion is made higher than that of the material forming the wiring material layer. It is desirable to execute a process for forming at least one selected from a fluoride, a chloride, and a nitride of the material forming the wiring material layer into the surface portion of the wiring material layer.
    Type: Grant
    Filed: March 22, 2004
    Date of Patent: January 4, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keiichi Sasaki, Masato Kamiichi, Ershad Ali Chowdhury, Yukihiro Hayakawa
  • Publication number: 20040235234
    Abstract: A semiconductor device comprises a first substrate including an element, a first plug penetrating through the first substrate, made of a conductive material, and electrically connected with the element, a second substrate provided above the first substrate, and electrically connected with the element via the first plug, and a second plug penetrating through the first substrate, made of a non-dielectric material, and being not electrically connected with the second substrate.
    Type: Application
    Filed: June 25, 2004
    Publication date: November 25, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kanako Sawada, Keiichi Sasaki
  • Patent number: 6809421
    Abstract: A multichip semiconductor device is disclosed in which chips are stacked each of which comprises a semiconductor substrate formed on top with circuit components and an interlayer insulating film formed on the top of the semiconductor substrate. At least one of the chips has a connect plug of a metal formed in a through hole that passes through the semiconductor substrate and the interlayer insulating film. The chip with the connect plug is electrically connected with another chip by that connect plug.
    Type: Grant
    Filed: August 20, 1999
    Date of Patent: October 26, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuo Hayasaka, Katsuya Okumura, Keiichi Sasaki, Mie Matsuo
  • Publication number: 20040191982
    Abstract: A circuit board for a liquid discharging apparatus in which coating performance of a protective layer and a cavitation resistive film on a heat generating element is excellent and durability is excellent and a manufacturing method of such a circuit board are provided. A surface portion of a wiring material layer is processed so that an etching speed of the surface portion is made higher than that of the material forming the wiring material layer. It is desirable to execute a process for forming at least one selected from a fluoride, a chloride, and a nitride of the material forming the wiring material layer into the surface portion of the wiring material layer.
    Type: Application
    Filed: March 22, 2004
    Publication date: September 30, 2004
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Keiichi Sasaki, Masato Kamiichi, Ershad Ali Chowdhury, Yukihiro Hayakawa
  • Patent number: 6751577
    Abstract: In a method of degradation diagnosis according to the present invention, an equipment degradation diagnosis request is input through network 4 from a diagnosis requester and a degradation diagnosis requests handler is selected in accordance with execution condition information of degradation diagnosis specified in respect of at least one degradation diagnosis requests handler and condition information in accordance with which an diagnosis requester requests degradation diagnosis. A request for execution of degradation diagnosis is made to this selected degradation diagnosis requests handler and the results of execution of the degradation diagnosis obtained by the selected degradation diagnosis requests handler are acquired and output through network 4 to the diagnosis requester. In this way, a service can be implemented whereby diagnosis of degradation requested by a diagnosis requester from a diagnostic service provider is performed rapidly and easily at low cost.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: June 15, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiichi Sasaki, Akira Sawada, Yoko Todo, Katsumi Kanehira, Kazushige Kimura, Kenji Adachi, Masaaki Ookubo, Tadayoshi Murayama, Hiromi Imai
  • Patent number: 6709966
    Abstract: A semiconductor device comprising the bump containing magnetic body, magnetic body, the bump including non-magnetic body for at least partially covering the magnetic body, mixture of magnetic particles and non-magnetic particles and the bump including baked magnetic particles and baked non-magnetic particles.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: March 23, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshimi Hisatsune, Keiichi Sasaki, Hiroshi Ikegami, Mie Matsuo, Nobuo Hayasaka, Katsuya Okumura
  • Publication number: 20040043596
    Abstract: Form a trench in a major surface of a semiconductor substrate, then bury a paste in the trench. The paste contains solids having a conductive substance and a resin, and solvent for dissolving the resin. The solids content of the paste is not less than 60 vol % and a viscosity ratio thereof is not more than 2.
    Type: Application
    Filed: August 25, 2003
    Publication date: March 4, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Keiichi Sasaki, Manabu Kimura, Yoshimi Hisatsune, Nobuo Hayasaka
  • Patent number: 6657306
    Abstract: Form a trench in a major surface of a semiconductor substrate, then bury a paste in the trench. The paste contains solids having a conductive substance and a resin, and solvent for dissolving the resin. The solids content of the paste is not less than 60 vol % and a viscosity ratio thereof is not more than 2.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: December 2, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiichi Sasaki, Manabu Kimura, Yoshimi Hisatsune, Nobuo Hayasaka