Abstract: An equipment main bod includes an intermediate electrode set disposed between upper and lower welding electrodes and provided at at least one of the upper and lower welding electrode sides. The intermediate electrode set includes a plurality of intermediate units, each intermediate unit having an intermediate electrode set jig and an intermediate electrode attachable to and detachable from the intermediate electrode set jig, and is configured as a rotary type in which the plurality of intermediate units are provided so as to be rotatable in a circumferential direction such that the plurality of intermediate units sequentially stop at a welding position that is aligned with the upper and lower welding electrodes in an up-down direction. The intermediate electrode set is configured to resistance-weld the workpiece, while pressing the workpiece by the pressing unit, via the intermediate electrode of the intermediate unit at the welding position.

Abstract: A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The gate insulating film is provided on the first main surface. The silicon carbide substrate includes a first body region having p type, a second body region having p type, and a JFET region provided between the first body region and the second body region and having n type. The JFET region has both a first impurity capable of providing the p type and a second impurity capable of providing the n type. A concentration of the second impurity is higher than a concentration of the first impurity. The silicon carbide semiconductor device capable of suppressing dielectric breakdown of the gate insulating film is provided.

Abstract: A method for manufacturing a silicon carbide epitaxial substrate includes epitaxially growing a first layer on a silicon carbide single crystal substrate, and forming a second layer at an outermost surface of the first layer. The second layer has a chemical composition or density different from that of the first layer. A ratio of a thickness of the second layer to a thickness of the first layer is more than 0% and less than or equal to 10%.

Abstract: A silicon carbide film has first and second main surfaces. The second main surface has an element formation surface and a termination surface. The silicon carbide film has a first range that constitutes a first main surface and an intermediate surface opposite to the first main surface, and a second range that is provided on the intermediate surface and constitutes the element formation surface. The first range includes: a first breakdown voltage holding layer, and a guard ring region partially provided at the intermediate surface in the termination portion. The second range has a second breakdown voltage holding layer. The second range has one of a structure only having the second breakdown voltage holding layer in the termination portion and a structure disposed only in the element portion of the element portion and the termination portion.

Abstract: A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The gate insulating film is provided on the first main surface. The silicon carbide substrate includes a first body region having p type, a second body region having p type, and a JFET region provided between the first body region and the second body region and having n type. The JFET region has both a first impurity capable of providing the p type and a second impurity capable of providing the n type. A concentration of the second impurity is higher than a concentration of the first impurity. The silicon carbide semiconductor device capable of suppressing dielectric breakdown of the gate insulating film is provided.

Abstract: A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. The silicon carbide single crystal substrate has a first main surface. The silicon carbide layer is on the first main surface. The silicon carbide layer includes a second main surface opposite to a surface thereof in contact with the silicon carbide single crystal substrate. The second main surface has a maximum diameter of more than or equal to 100 mm. The second main surface includes an outer peripheral region which is within 3 mm from an outer edge of the second main surface, and a central region surrounded by the outer peripheral region. The central region has a haze of less than or equal to 75 ppm.

Abstract: The method for manufacturing a laminated metal foil (1) according to the present invention includes: a first step of forming, in a weld site (A) of laminated layers of a metal foil (2), by the use of a cutter (C) whose longitudinal cross-sectional shape is a substantially V-shape, a notch (3) that is linear in a planar view and penetrates the laminated layers of the metal foil (2) in a lamination direction (S), to cause the laminated layers of the metal foil (2) to bond to each other along the lamination direction (S) at ends (3a) of a linear notch; and a second step of bringing an electrode (E) for resistance welding into press-contact with the weld site (A) and then energizing the weld site (A) via the electrode (E), to perform resistance welding on the laminated metal foil (1).

Abstract: A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. In a direction parallel to a central region, a ratio of a standard deviation of a carrier concentration of the silicon carbide layer to an average value of the carrier concentration of the silicon carbide layer is less than 5%. The average value of the carrier concentration is more than or equal to 1×1014cm?3 and less than or equal to 5×1016cm?3. In the direction parallel to the central region, a ratio of a standard deviation of a thickness of the silicon carbide layer to an average value of the thickness of the silicon carbide layer is less than 5%. The central region has an arithmetic mean roughness (Sa) of less than or equal to 1 nm. The central region has a haze of less than or equal to 50.

Abstract: A silicon carbide epitaxial substrate has a silicon carbide single-crystal substrate and a silicon carbide layer. An average value of carrier concentration in the silicon carbide layer is not less than 1×1015 cm?3 and not more than 5×1016 cm?3. In-plane uniformity of the carrier concentration is not more than 2%. The second main surface has: a groove 80 extending in one direction along the second main surface, a width of the groove in the one direction being twice or more as large as a width thereof in a direction perpendicular to the one direction, and a maximum depth of the groove from the second main surface being not more than 10 nm; and a carrot defect. A value obtained by dividing a number of the carrot defects by a number of the grooves is not more than 1/500.

Abstract: In forming of a silicon carbide layer, when an X axis indicates a first value representing, in percentage, a value obtained by dividing a flow rate of silane by a flow rate of hydrogen and a Y axis indicates a second value representing a flow rate of ammonia in sccm, the first value and the second value fall within a quadrangular region surrounded by first coordinates, second coordinates, third coordinates, and fourth coordinates in XY plane coordinates. The first coordinates are (0.05, 6.5×10?4). The second coordinates are (0.05, 4.5×10?3). The third coordinates are (0.22, 1.2×10?2). The fourth coordinates are (0.22, 1.3×10?1). After the forming of the silicon carbide layer, an average value of carrier concentration of the silicon carbide layer is more than or equal to 1×1015 cm?3 and less than or equal to 2×1016 cm?3.

Abstract: A silicon carbide epitaxial substrate includes: a silicon carbide single crystal substrate; and an epitaxial layer. The silicon carbide single crystal substrate has a diameter of not less than 100 mm. The epitaxial layer has a thickness of not less than 10 ?m. The epitaxial layer has a carrier concentration of not less than 1×1014 cm?3 and not more than 1×1016 cm?3. A ratio of a standard deviation of the carrier concentration in a plane of the epitaxial layer to an average value of the carrier concentration in the plane is not more than 10%. The epitaxial layer has a main surface. The main surface has an arithmetic mean roughness Sa of not more than 0.3 nm. An area density of pits originated from a threading screw dislocation is not more than 1000 cm?2. Each of the pits has a maximum depth of not less than 8 nm.

Abstract: A semiconductor device has a semiconductor layer and a substrate. The semiconductor layer constitutes at least a part of a current path, and is made of silicon carbide. The substrate has a first surface supporting the semiconductor layer, and a second surface opposite to the first surface. Further, the substrate is made of silicon carbide having a 4H type single-crystal structure. Further, the substrate has a physical property in which a ratio of a peak strength in a wavelength of around 500 nm to a peak strength in a wavelength of around 390 nm is 0.1 or smaller in photoluminescence measurement. In this way, the semiconductor device is obtained to have a low on-resistance.

Abstract: A semiconductor device has a semiconductor layer and a substrate. The semiconductor layer constitutes at least a part of a current path, and is made of silicon carbide. The substrate has a first surface supporting the semiconductor layer, and a second surface opposite to the first surface. Further, the substrate is made of silicon carbide having a 4H type single-crystal structure. Further, the substrate has a physical property in which a ratio of a peak strength in a wavelength of around 500 nm to a peak strength in a wavelength of around 390 nm is 0.1 or smaller in photoluminescence measurement. In this way, the semiconductor device is obtained to have a low on-resistance.

Abstract: A method for manufacturing a silicon carbide epitaxial substrate includes epitaxially growing a first layer on a silicon carbide single crystal substrate, and forming a second layer at an outermost surface of the first layer. The second layer has a chemical composition or density different from that of the first layer. A ratio of a thickness of the second layer to a thickness of the first layer is more than 0% and less than or equal to 10%.

Abstract: A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The gate insulating film is provided on the first main surface. The silicon carbide substrate includes a first body region having p type, a second body region having p type, and a JFET region provided between the first body region and the second body region and having n type. The JFET region has both a first impurity capable of providing the p type and a second impurity capable of providing the n type. A concentration of the second impurity is higher than a concentration of the first impurity. The silicon carbide semiconductor device capable of suppressing dielectric breakdown of the gate insulating film is provided.

Abstract: An SiC semiconductor device includes an SiC layer including a drift region forming a surface and a body region forming a part of a surface and being in contact with the drift region, a drain electrode electrically connected to a region on a side of the surface in the drift region, and a source electrode electrically connected to the body region. Main carriers which pass through the drift region and migrate between the drain electrode and the source electrode are only electrons. Z1/2 center is introduced into the drift region at a concentration not lower than 1×1013 cm?3 and not higher than 1×1015 cm?3.

Abstract: A semiconductor laminate includes a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, and an epitaxial layer composed of silicon carbide disposed on the first main surface. The second main surface has an average value of roughness Ra of 0.1 ?m or more and 1 ?m or less with a standard deviation of 25% or less of the average value.