Patents by Inventor Keiji Watanabe

Keiji Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170362082
    Abstract: First, an ion beam is applied to a workpiece to form a tapered hole the side wall of which is inclined. Next, the application of the ion beam is stopped, and then a material gas is introduced from the gas source to the upper surface of the workpiece from an oblique direction to cause gas molecules to be adsorbed to the upper surface of the workpiece and to the upper portion of the side wall of the hole. Next, introduction of the material gas is stopped, and then the ion beam is applied again to the region of the workpiece where the hole is formed. As a result, at the upper portion of the side wall of the hole, film formation occurs using the gas molecules as the material adsorbed to the side wall of the hole, and, at the bottom portion of the hole, etching of the workpiece occurs.
    Type: Application
    Filed: June 1, 2017
    Publication date: December 21, 2017
    Inventors: Keiji WATANABE, Shuntaro MACHIDA, Katsuya MIURA, Aki TAKEI, Tetsufumi KAWAMURA, Nobuyuki SUGII, Daisuke RYUZAKI
  • Publication number: 20170338372
    Abstract: A configuration of a display device capable of color display is obtained. The display device includes a plurality of rod-shaped light-emitting elements each of which includes a semiconductor and which emit light beams having wavelength distributions different from each other, and alignment electrodes (12). The alignment electrodes (12) include a first electrode pair (12a), a second electrode pair (12b), and a third electrode pair (12c).
    Type: Application
    Filed: November 18, 2015
    Publication date: November 23, 2017
    Inventors: Nobuaki TERAGUCHI, Takuya SATO, Keiji WATANABE, Kohichiroh ADACHI, Akihide SHIBATA, Hiroshi IWATA
  • Patent number: 9714262
    Abstract: A composition for forming a passivation layer, comprising a compound represented by Formula (I): M(OR1)m. In Formula (I), M comprises at least one metal element selected from the group consisting of Nb, Ta, V, Y and Hf, each R1 independently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: July 25, 2017
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Shuichiro Adachi, Masato Yoshida, Takeshi Nojiri, Yasushi Kurata, Tooru Tanaka, Akihiro Orita, Tsuyoshi Hayasaka, Takashi Hattori, Mieko Matsumura, Keiji Watanabe, Masatoshi Morishita, Hirotaka Hamamura
  • Patent number: 9610773
    Abstract: A method for producing a liquid-ejection-head substrate includes providing a substrate having an energy-generating element and a pad, the pad including a wiring layer, the wiring layer in the pad having a relatively thick portion and a relatively thin portion and performing electrical inspection by applying a contact probe to the relatively thin portion of the wiring layer in the pad.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: April 4, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Satoshi Ibe, Keiji Watanabe, Junya Hayasaka, Shiro Sujaku, Kouji Hasegawa
  • Patent number: 9608083
    Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: March 28, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Masahito Kanamura, Norikazu Nakamura, Toyoo Miyajima, Masayuki Takeda, Keiji Watanabe, Toshihide Kikkawa, Kenji Imanishi, Toshihiro Ohki, Tadahiro Imada
  • Patent number: 9595630
    Abstract: An encapsulating material for solar cell containing an ethylene/?-olefin copolymer satisfying the following a1) and a2), and a specific peroxyketal having a 1-hour half-life temperature in a range of 100 to 135 degrees centigrade; the peroxyketal being contained in an amount of 0.1 to less than 0.8 weight parts relative to 100 weight parts of the ethylene/?-olefin copolymer. a1) the shore A hardness is from 60 to 85 as measured in accordance with ASTM D2240. a2) MFR is from 2 to 50 g/10 minutes as measured under the conditions of a temperature of 190 degrees centigrade and a load of 2.16 kg in accordance with ASTM D1238.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: March 14, 2017
    Assignee: MITSUI CHEMICALS TOHCELLO, INC.
    Inventors: Shigenobu Ikenaga, Fumito Takeuchi, Keiji Watanabe, Tomoaki Ito
  • Publication number: 20160229184
    Abstract: A method for producing a liquid-ejection-head substrate includes providing a substrate having an energy-generating element and a pad, the pad including a wiring layer, the wiring layer in the pad having a relatively thick portion and a relatively thin portion and performing electrical inspection by applying a contact probe to the relatively thin portion of the wiring layer in the pad.
    Type: Application
    Filed: February 2, 2016
    Publication date: August 11, 2016
    Inventors: Satoshi Ibe, Keiji Watanabe, Junya Hayasaka, Shiro Sujaku, Kouji Hasegawa
  • Publication number: 20160229183
    Abstract: A method for manufacturing a liquid-discharge-head substrate includes providing a substrate having an energy-generating element and a pad, the pad having a wiring layer and a contact-probe receiving section, the contact-probe receiving section having a Vickers hardness that is higher than a Vickers hardness of the wiring layer; bringing a contact probe into contact with the contact-probe receiving section; and performing an electrical inspection by bringing the contact probe into contact with the wiring layer in the pad.
    Type: Application
    Filed: February 1, 2016
    Publication date: August 11, 2016
    Inventors: Shiro Sujaku, Keiji Watanabe, Kouji Hasegawa, Junya Hayasaka, Satoshi Ibe
  • Publication number: 20160211389
    Abstract: A composition for forming a passivation layer, including a resin and a compound represented by Formula (I): M(OR1)m. In Formula (I), M includes at least one metal element selected from the group consisting of Nb, Ta, V, Y and Hf, each R1 independently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5.
    Type: Application
    Filed: March 24, 2016
    Publication date: July 21, 2016
    Inventors: Tooru TANAKA, Masato YOSHIDA, Takeshi NOJIRI, Yasushi KURATA, Akihiro ORITA, Shuichiro ADACHI, Tsuyoshi HAYASAKA, Takashi HATTORI, Mieko MATSUMURA, Keiji WATANABE, Masatoshi MORISHITA, Hirotaka HAMAMURA
  • Patent number: 9387675
    Abstract: A liquid discharge head includes a substrate, a heat resistor layer, and a side wall member that forms a side wall of a pressure chamber. The heat resistor layer has a heat effect portion configured to foam liquid in an interior of the pressure chamber to discharge liquid from a discharge port. The heat effect portion is apart from the substrate, at least part of a surface of the heat resistor layer is covered with a covering layer in the interior of the pressure chamber, and the covering layer extends from the interior of the pressure chamber to a position coming into contact with the side wall of the side wall member.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: July 12, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Makoto Watanabe, Keiji Watanabe, Shuhei Oya, Shingo Nagata
  • Patent number: 9358786
    Abstract: A recording head having a substrate and a channel forming member configured to form a flow channel, a supply port formed at the substrate so as to penetrate through the substrate, the flow channel communicates with the supply port, and a member formed of an organic material and configured to connect two surfaces forming the supply port and opposing each other with the supply port interposed therebetween.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: June 7, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keiji Watanabe, Yoshinori Tagawa
  • Patent number: 9349895
    Abstract: An encapsulating material for solar cell excellent in a balance among properties including transparency, flexibility, adhesiveness, heat resistance, appearance, crosslinking properties, electrical properties and calender moldability. The encapsulating material includes an ethylene/?-olefin copolymer satisfying the following requirements: (a1) the content ratio of structural units derived from ethylene is from 80 to 90 mol % and the content ratio of structural units derived from ?-olefin having 3 to 20 carbon atoms is from 10 to 20 mol %; (a2) MFR is equal to or more than 2 g/10 minutes and less than 10 g/10 minutes as measured under the conditions of a temperature of 190 degrees centigrade and a load of 2.16 kg in accordance with ASTM D1238; (a3) the density is from 0.865 to 0.884 g/cm3 as measured in accordance with ASTM D1505; and (a4) the shore A hardness is from 60 to 85 as measured in accordance with ASTM D2240.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: May 24, 2016
    Assignees: MITSUI CHEMICALS, INC., MITSUI CHEMICALS TOHCELLO, INC.
    Inventors: Shigenobu Ikenaga, Fumito Takeuchi, Keiji Watanabe, Tomoaki Ito
  • Patent number: 9324808
    Abstract: A semiconductor device, includes a semiconductor layer formed above a substrate; an insulating film formed on the semiconductor layer; and an electrode formed on the insulating film. The insulating film has a membrane stress at a side of the semiconductor layer lower than a membrane stress at a side of the electrode.
    Type: Grant
    Filed: May 25, 2013
    Date of Patent: April 26, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Norikazu Nakamura, Shirou Ozaki, Masayuki Takeda, Keiji Watanabe
  • Patent number: 9257583
    Abstract: A solar cell including a substrate 1, a nanopillar 11 having diameter D1 connected to the substrate 1, and a nanopillar 12 having diameter D2 connected to the substrate 1 is characterized in that D2 is greater than D1 in order to realize a solar cell having, as the surface structure, a nanopillar array structure with which it is possible to prevent reflection within the broad wavelength region of solar light. A nanopillar array structure 21 formed from two types of nanopillars having different diameters has a point of minimum reflectivity of a nanopillar array structure formed from the nanopillar 11 having diameter D1 and a point of minimum reflectivity of a nanopillar array structure formed from the nanopillar 12 having diameter D2 and therefore, is capable of preventing reflection within the broad wavelength region of solar light.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: February 9, 2016
    Assignee: HITACHI, LTD.
    Inventors: Keiji Watanabe, Ryuta Tsuchiya, Takashi Hattori, Mieko Matsumura
  • Publication number: 20150343780
    Abstract: A liquid discharge head includes a substrate, a heat resistor layer, and a side wall member that forms a side wall of a pressure chamber. The heat resistor layer has a heat effect portion configured to foam liquid in an interior of the pressure chamber to discharge liquid from a discharge port. The heat effect portion is apart from the substrate, at least part of a surface of the heat resistor layer is covered with a covering layer in the interior of the pressure chamber, and the covering layer extends from the interior of the pressure chamber to a position coming into contact with the side wall of the side wall member.
    Type: Application
    Filed: May 26, 2015
    Publication date: December 3, 2015
    Inventors: Makoto Watanabe, Keiji Watanabe, Shuhei Oya, Shingo Nagata
  • Publication number: 20150328891
    Abstract: A recording head having a substrate and a channel forming member configured to form a flow channel, a supply port formed at the substrate so as to penetrate through the substrate, the flow channel communicates with the supply port, and a member formed of an organic material and configured to connect two surfaces forming the supply port and opposing each other with the supply port interposed therebetween.
    Type: Application
    Filed: May 8, 2015
    Publication date: November 19, 2015
    Inventors: Keiji Watanabe, Yoshinori Tagawa
  • Publication number: 20150279956
    Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.
    Type: Application
    Filed: June 9, 2015
    Publication date: October 1, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Masahito Kanamura, Norikazu Nakamura, Toyoo Miyajima, Masayuki Takeda, Keiji Watanabe, Toshihide Kikkawa, Kenji Imanishi, Toshihiro Ohki, Tadahiro Imada
  • Publication number: 20150228812
    Abstract: A composition for forming a passivation layer, including a resin and a compound represented by Formula (I): M(OR1)m. In Formula (I), M includes at least one metal element selected from the group consisting of Nb, Ta, V, Y and Hf, each R1 independently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5.
    Type: Application
    Filed: July 19, 2013
    Publication date: August 13, 2015
    Inventors: Tooru Tanaka, Masato Yoshida, Takeshi Nojira, Yasushi Kurata, Akihiro Orita, Shuichiro Adachi, Tsuyoshi Hayasaka, Takashi Hattori, Mieko Matsumura, Keiji Watanabe, Masatoshi Morishita, Hirotaka Hamamura
  • Publication number: 20150214391
    Abstract: A passivation film includes aluminum oxide and niobium oxide, and the passivation film is used in a photovoltaic cell element having a silicon substrate. A photovoltaic cell element includes: a p-type silicon substrate 1 that comprises monocrystalline silicon or polycrystalline silicon; an n-type impurity diffusion layer 2 that is formed on a light receiving surface of the silicon substrate 1; a first electrode 5 that is formed on the n-type impurity diffusion layer 2; a second electrode 6 that is formed on the back surface of the silicon substrate 1; a passivation film 7 that is formed on the back surface of the silicon substrate 1, the passivation film 7 having plural openings OA and including aluminum oxide and niobium oxide. The second electrode 6 is electrically connected to the back surface of the silicon substrate 1 through the plural openings OA.
    Type: Application
    Filed: July 19, 2013
    Publication date: July 30, 2015
    Inventors: Takashi Hattori, Mieko Matsumura, Keiji Watanabe, Masatoshi Morishita, Hirotaka Hamamura
  • Patent number: 9082756
    Abstract: A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: July 14, 2015
    Assignee: Fujitsu Limited
    Inventors: Kozo Shimizu, Keishiro Okamoto, Nobuhiro Imaizumi, Tadahiro Imada, Keiji Watanabe