Abstract: A composition for forming a passivation layer, comprising a compound represented by Formula (I): M(OR1)m. In Formula (I), M comprises at least one metal element selected from the group consisting of Nb, Ta, V, Y and Hf, each R1 independently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5.

Abstract: A solar-cell sealant that has excellent properties such as transparency, flexibility, adhesiveness, heat resistance, appearance, cross-linking characteristics, electrical characteristics, and calenderability. A solar-cell sealant that contains an ethylene/?-olefin/unconjugated-polyene copolymer satisfying requirements (a1) through (a3). Requirement (a1) is that constituent units derived from ethylene constitute 80-90 mol %, constituent units derived from C3-20 ?-olefin constitute 9.99-19.99 mol %, and constituent units derived from an unconjugated polyene constitute 0.01-5.0 mol % of said copolymer. Requirement (a2) is that the MFR of said copolymer, as measured in accordance with ASTM D1238 at 190° C. under a 2.16 kg load, be at least 2 g/10 min. and less than 10 g/10 min. Requirement (a3) is that the Shore A hardness of said copolymer, as measured in accordance with ASTM D2240, be 60 to 85.

Abstract: A surface reflectivity of a solar cell is reduced by applying a nanopillar array including a plurality of nanopillars to the solar cell. Further, by constituting the nanopillars with a Si/SiGe superlattice and controlling a Ge composition ratio of a SiGe layer (2), excited electron and hole are spatially separated in different layers, thus increasing a carrier lifetime, and at the same time, an optical-electrical conversion efficiency is improved by a multi-exciton phenomenon due to a quantum confinement effect. In addition, by forming an intermediate band by thinning a Si layer (1) and the SiGe layer (2), a carrier extraction efficiency is improved.

Abstract: A semiconductor device may include a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a source electrode and a drain electrode in contact with the first semiconductor layer or the second semiconductor layer, an opening formed in the second semiconductor layer, an insulating film formed on an inner surface of the opening formed in the second semiconductor layer and above the second semiconductor layer, a gate electrode formed in the opening via the insulating film, and a protective film formed on the insulating film and including an amorphous film containing carbon as a major component.

Abstract: Provided is a method of manufacturing a substrate for a liquid discharge head including a first face, energy generating elements which generate the energy to be used to discharge a liquid to a second face opposite to the first face, and liquid supply ports for supplying the liquid to the energy generating elements. The method includes preparing a silicon substrate having, at the first face, an etching mask layer having an opening corresponding to a portion where the liquid supply ports are to be formed, and having first recesses provided within the opening, and second recesses provided in the region of the second face where the liquid supply ports are to be formed, the first recesses and the second recesses being separated from each other by a portion of the substrate; and etching the silicon substrate by crystal anisotropic etching from the opening of the first face to form the liquid supply ports.

Abstract: In the existent method for manufacturing a solar cell, manufacture of a solar cell having a quantum well having a crystalline well layer and capable of controlling the thickness of the well layer was difficult. A quantum well having an amorphous well layer, comprising a barrier layer and an amorphous well layer is formed and then the quantum well having the amorphous well layer is annealed thereby crystallizing the amorphous well layer to form a quantum well having a crystalline well layer. By applying energy density applied to the amorphous well layer at an energy density of 1.26 J/mm2 or more and 28.8 J/mm2 or less, the crystalline well layer can be formed and the lamination structure of the quantum well can be maintained simultaneously.

Abstract: A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.

Abstract: An encapsulating material for solar cell containing an ethylene/?-olefin copolymer satisfying the following a1) and a2), and a specific peroxyketal having a 1-hour half-life temperature in a range of 100 to 135 degrees centigrade; the peroxyketal being contained in an amount of 0.1 to less than 0.8 weight parts relative to 100 weight parts of the ethylene/?-olefin copolymer. a1) the shore A hardness is from 60 to 85 as measured in accordance with ASTM D2240. a2) MFR is from 2 to 50 g/10 minutes as measured under the conditions of a temperature of 190 degrees centigrade and a load of 2.

Abstract: Disclosed is an encapsulating material for solar cell containing an ethylene/?-olefin copolymer satisfying the following requirements (a1) to (a4): (a1) the content ratio of structural units derived from ethylene is from 80 to 90 mol % and the content ratio of structural units derived from ?-olefin having 3 to 20 carbon atoms is from 10 to 20 mol %; (a2) MFR is from 10 to 50 g/10 minutes as measured under the conditions of a temperature of 190 degrees centigrade and a load of 2.16 kg in accordance with ASTM D1238; (a3) the density is from 0.865 to 0.884 g/cm3 as measured in accordance with ASTM D1505; and (a4) the shore A hardness is from 60 to 85 as measured in accordance with ASTM D2240.

Abstract: A solar cell including a substrate 1, a nanopillar 11 having diameter D1 connected to the substrate 1, and a nanopillar 12 having diameter D2 connected to the substrate 1 is characterized in that D2 is greater than D1 in order to realize a solar cell having, as the surface structure, a nanopillar array structure with which it is possible to prevent reflection within the broad wavelength region of solar light. A nanopillar array structure 21 formed from two types of nanopillars having different diameters has a point of minimum reflectivity of a nanopillar array structure formed from the nanopillar 11 having diameter D1 and a point of minimum reflectivity of a nanopillar array structure formed from the nanopillar 12 having diameter D2 and therefore, is capable of preventing reflection within the broad wavelength region of solar light.

Abstract: A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.

Abstract: A method for manufacturing a substrate for liquid-ejecting heads includes etching a surface of a silicon substrate using a first etchant, with a silicon oxide layer as a mask, to form a depression as a part of a liquid supply port, and subsequently etching at least the silicon oxide layer and the thickness sandwiched between the depression and the etched surface of the silicon substrate with a second etchant to form the liquid supply port.

Abstract: A method for manufacturing a semiconductor device includes placing a sheet containing a fibrous material having at least one outer surface having a metal on a semiconductor chip-mounting region of a substrate; forming a bonding layer containing a fusible metal on the semiconductor chip-mounting region; placing a semiconductor chip on the semiconductor chip-mounting region; and bonding the semiconductor chip to the semiconductor chip-mounting region with the fusible metal-containing bonding layer by heating.

Abstract: According to an embodiment, coordination list-providing system is provided. The coordination list-providing system comprises a product list display unit configured to display on a display screen product information including a product image, and a product name for each of one or more products. The coordination list-providing system further comprises a detailed information display unit configured to display on the display screen detailed information of a selected product that is selected from the one or more products. The coordination list-providing system further comprises a coordination list unit configured to provide a coordination list comprising one or more coordination images of coordinating products associated with the selected product when a predetermined operation is performed.

Abstract: A semiconductor device, includes a semiconductor layer formed above a substrate; an insulating film formed on the semiconductor layer; and an electrode formed on the insulating film. The insulating film has a membrane stress at a side of the semiconductor layer lower than a membrane stress at a side of the electrode.

Abstract: A semiconductor device may include a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a source electrode and a drain electrode in contact with the first semiconductor layer or the second semiconductor layer, an opening formed in the second semiconductor layer, an insulating film formed on an inner surface of the opening formed in the second semiconductor layer and above the second semiconductor layer, a gate electrode formed in the opening via the insulating film, and a protective film formed on the insulating film and including an amorphous film containing carbon as a major component.

Abstract: A solar-cell sealant that has excellent properties such as transparency, flexibility, adhesiveness, heat resistance, appearance, cross-linking characteristics, electrical characteristics, and calenderability. A solar-cell sealant that contains an ethylene/?-olefin/unconjugated-polyene copolymer satisfying requirements (a1) through (a3). Requirement (a1) is that constituent units derived from ethylene constitute 80-90 mol %, constituent units derived from C3-20 ?-olefin constitute 9.99-19.99 mol %, and constituent units derived from an unconjugated polyene constitute 0.01-5.0 mol % of said copolymer. Requirement (a2) is that the MFR of said copolymer, as measured in accordance with ASTM D1238 at 190° C. under a 2.16 kg load, be at least 2 g/10 min. and less than 10 g/10 min. Requirement (a3) is that the Shore A hardness of said copolymer, as measured in accordance with ASTM D2240, be 60 to 85.

Abstract: An encapsulating material for solar cell excellent in a balance among properties including transparency, flexibility, adhesiveness, heat resistance, appearance, crosslinking properties, electrical properties and calender moldability. The encapsulating material includes an ethylene/?-olefin copolymer satisfying the following requirements: (a1) the content ratio of structural units derived from ethylene is from 80 to 90 mol % and the content ratio of structural units derived from ?-olefin having 3 to 20 carbon atoms is from 10 to 20 mol %; (a2) MFR is equal to or more than 2 g/10 minutes and less than 10 g/10 minutes as measured under the conditions of a temperature of 190 degrees centigrade and a load of 2.16 kg in accordance with ASTM D1238; (a3) the density is from 0.865 to 0.884 g/cm3 as measured in accordance with ASTM D1505; and (a4) the shore A hardness is from 60 to 85 as measured in accordance with ASTM D2240.

Abstract: A semiconductor device includes: a semiconductor chip including a nitride semiconductor layered structure including a carrier transit layer and a carrier supply layer; a first resin layer on the semiconductor chip, the first resin layer including a coupling agent; a second resin layer on the first resin layer, the second resin layer including a surfactant; and a sealing resin layer to seal the semiconductor chip with the first resin layer and the second resin layer.

Abstract: A semiconductor device, includes a semiconductor layer formed above a substrate; an insulating film formed on the semiconductor layer; and an electrode formed on the insulating film. The insulating film has a membrane stress at a side of the semiconductor layer lower than a membrane stress at a side of the electrode.