Patents by Inventor Keiji Watanabe

Keiji Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130167911
    Abstract: Disclosed is an encapsulating material for solar cell containing an ethylene/?-olefin copolymer satisfying the following requirements (a1) to (a4): (a1) the content ratio of structural units derived from ethylene is from 80 to 90 mol % and the content ratio of structural units derived from ?-olefin having 3 to 20 carbon atoms is from 10 to 20 mol %; (a2) MFR is from 10 to 50 g/10 minutes as measured under the conditions of a temperature of 190 degrees centigrade and a load of 2.16 kg in accordance with ASTM D1238; (a3) the density is from 0.865 to 0.884 g/cm3 as measured in accordance with ASTM D1505; and (a4) the shore A hardness is from 60 to 85 as measured in accordance with ASTM D2240.
    Type: Application
    Filed: October 7, 2011
    Publication date: July 4, 2013
    Applicant: MITSUI CHEMICALS, INC.
    Inventors: Shigenobu Ikenaga, Fumito Takeuchi, Keiji Watanabe, Jun Tokuhiro, Takanobu Murofushi, Kazuhiro Yarimizu, Tomoaki Ito, Nobuhiro Maruko
  • Patent number: 8449783
    Abstract: A liquid ejection head substrate is manufactured by forming a wiring pattern on one surface of a substrate, forming an etching mask layer on the other surface of the substrate, forming a positioning reference mark on the etching mask layer by means of a laser, forming an opening pattern groove running through the etching mask layer and having a bottom in the inside of the silicon substrate, using the positioning reference mark, and forming a liquid supply port running through the silicon substrate by etching the silicon substrate from the opening pattern groove to the one surface by means of crystal anisotropic etching.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: May 28, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Keiji Watanabe
  • Patent number: 8377828
    Abstract: A method of manufacturing a substrate for a liquid discharge head, the substrate being a silicon substrate having a first surface opposed to a second surface, the method comprising the steps of providing a layer on the second surface of the silicon substrate, wherein the layer has a lower etch rate than silicon when exposed to an etchant of silicon, partially removing the layer so as to expose part of the second surface of the silicon substrate, wherein the exposed part surrounds at least one part of the layer; and wet etching the layer and the exposed part of the second surface of the silicon substrate, using the etchant of silicon, to form a liquid supply port extending from the second surface to the first surface of the silicon substrate.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: February 19, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keiji Matsumoto, Shuji Koyama, Hiroyuki Abo, Keiji Watanabe
  • Publication number: 20130026130
    Abstract: A liquid ejection head substrate is manufactured by forming a wiring pattern on one surface of a substrate, forming an etching mask layer on the other surface of the substrate, forming a positioning reference mark on the etching mask layer by means of a laser, forming an opening pattern groove running through the etching mask layer and having a bottom in the inside of the silicon substrate, using the positioning reference mark, and forming a liquid supply port running through the silicon substrate by etching the silicon substrate from the opening pattern groove to the one surface by means of crystal anisotropic etching.
    Type: Application
    Filed: July 10, 2012
    Publication date: January 31, 2013
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Keiji Watanabe
  • Publication number: 20120318337
    Abstract: In a conventional solar cell, it has been difficult to ensure a sufficient light absorption and simultaneously to prevent current loss due to the reduction of the moving distance of electrons and holes. As a means for solving this difficulty, a plurality of a p-i-n junctions are stacked through an insulating film and are connected in parallel with each other using through-electrodes. In this case, the through-electrodes and the p-i-n junctions are connected through the p-layer or the n-layer, thereby moving electrons and holes in opposite directions and generating output current. In addition, the i-layer is made thicker than the p-layer and the n-layer in each of the p-i-n junctions, thereby ensuring a sufficient light absorption and simultaneously preventing current loss.
    Type: Application
    Filed: February 17, 2012
    Publication date: December 20, 2012
    Inventors: Keiji Watanabe, Takashi Hattori, Mieko Matsumura, Ryuta Tsuchiya, Mutsuko Hatano
  • Publication number: 20120211764
    Abstract: A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 23, 2012
    Applicant: FUJITSU LIMITED,
    Inventors: Keishiro OKAMOTO, Tadahiro IMADA, Nobuhiro IMAIZUMI, Keiji WATANABE
  • Publication number: 20120211901
    Abstract: A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.
    Type: Application
    Filed: January 23, 2012
    Publication date: August 23, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Kozo SHIMIZU, Keishiro Okamoto, Nobuhiro Imaizumi, Tadahiro Imada, Keiji Watanabe
  • Publication number: 20120211899
    Abstract: A method for manufacturing a semiconductor device includes placing a sheet containing a fibrous material having at least one outer surface having a metal on a semiconductor chip-mounting region of a substrate; forming a bonding layer containing a fusible metal on the semiconductor chip-mounting region; placing a semiconductor chip on the semiconductor chip-mounting region; and bonding the semiconductor chip to the semiconductor chip-mounting region with the fusible metal-containing bonding layer by heating.
    Type: Application
    Filed: January 23, 2012
    Publication date: August 23, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Nobuhiro IMAIZUMI, Keishiro Okamoto, Keiji Watanabe
  • Publication number: 20120205662
    Abstract: A semiconductor device includes: a semiconductor layer formed over a substrate; an insulating film formed over the semiconductor layer; and an electrode formed over the insulating film, wherein the insulating film includes an amorphous film including carbon.
    Type: Application
    Filed: January 25, 2012
    Publication date: August 16, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Norikazu Nakamura, Shirou Ozaki, Masayuki Takeda, Toyoo Miyajima, Toshihiro Ohki, Masahito Kanamura, Kenji Imanishi, Toshihide Kikkawa, Keiji Watanabe
  • Publication number: 20120205663
    Abstract: A semiconductor device, includes a semiconductor layer formed above a substrate; an insulating film formed on the semiconductor layer; and an electrode formed on the insulating film. The insulating film has a membrane stress at a side of the semiconductor layer lower than a membrane stress at a side of the electrode.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 16, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Norikazu NAKAMURA, Shirou OZAKI, Masayuki TAKEDA, Keiji WATANABE
  • Publication number: 20120208351
    Abstract: A cleaning apparatus for a semiconductor manufacturing apparatus includes: a oxide removal unit that removes an oxide over a surface of a deposit adhered to components of the semiconductor manufacturing apparatus, and a deposit removal unit that removes the deposit after the oxide over the surface is removed by the oxide removal unit.
    Type: Application
    Filed: January 25, 2012
    Publication date: August 16, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Norikazu Nakamura, Atsushi Yamada, Masayuki Takeda, Keiji Watanabe, Kenji Imanishi
  • Publication number: 20120199991
    Abstract: A semiconductor device includes: a semiconductor chip including a nitride semiconductor layered structure including a carrier transit layer and a carrier supply layer; a first resin layer on the semiconductor chip, the first resin layer including a coupling agent; a second resin layer on the first resin layer, the second resin layer including a surfactant; and a sealing resin layer to seal the semiconductor chip with the first resin layer and the second resin layer.
    Type: Application
    Filed: December 20, 2011
    Publication date: August 9, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Keishiro OKAMOTO, Tadahiro Imada, Nobuhiro Imaizumi, Keiji Watanabe
  • Publication number: 20120149143
    Abstract: In the existent method for manufacturing a solar cell, manufacture of a solar cell having a quantum well having a crystalline well layer and capable of controlling the thickness of the well layer was difficult. A quantum well having an amorphous well layer, comprising a barrier layer and an amorphous well layer is formed and then the quantum well having the amorphous well layer is annealed thereby crystallizing the amorphous well layer to form a quantum well having a crystalline well layer. By applying energy density applied to the amorphous well layer at an energy density of 1.26 J/mm2 or more and 28.8 J/mm2 or less, the crystalline well layer can be formed and the lamination structure of the quantum well can be maintained simultaneously.
    Type: Application
    Filed: November 23, 2011
    Publication date: June 14, 2012
    Applicant: Hitachi, Ltd.
    Inventors: Keiji WATANABE, Toshiyuki MINE, Akio SHIMA, Tomoko SEKIGUCHI, Ryuta TSUCHIYA
  • Publication number: 20120097637
    Abstract: Provided is a method of manufacturing a substrate for a liquid discharge head including a first face, energy generating elements which generate the energy to be used to discharge a liquid to a second face opposite to the first face, and liquid supply ports for supplying the liquid to the energy generating elements. The method includes preparing a silicon substrate having, at the first face, an etching mask layer having an opening corresponding to a portion where the liquid supply ports are to be formed, and having first recesses provided within the opening, and second recesses provided in the region of the second face where the liquid supply ports are to be formed, the first recesses and the second recesses being separated from each other by a portion of the substrate; and etching the silicon substrate by crystal anisotropic etching from the opening of the first face to form the liquid supply ports.
    Type: Application
    Filed: July 29, 2010
    Publication date: April 26, 2012
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Keiji Watanabe, Shuji Koyama, Hiroyuki Abo, Keiji Matsumoto
  • Publication number: 20120091522
    Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.
    Type: Application
    Filed: October 19, 2011
    Publication date: April 19, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, Masahito Kanamura, Norikazu Nakamura, Toyoo Miyajima, Masayuki Takeda, Keiji Watanabe, Toshihide Kikkawa, Kenji Imanishi, Toshihiro Ohki, Tadahiro Imada
  • Patent number: 8152276
    Abstract: A liquid ejecting head includes a coating resin layer including a plurality of ejection outlets for ejecting liquid and flow paths which are in fluid communication with the ejection outlets, respectively; a substrate having energy generating elements for generating energy for ejecting liquid; and an adhesion improving layer provided between the coating resin layer and the substrate. The coating resin layer further includes a first resin material layer closest to the substrate and at least one second resin material layer, and the first resin material layer provides at least one stepped portion continuing from a periphery of the second resin material layer.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: April 10, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroyuki Murayama, Yoshinori Tagawa, Souta Takeuchi, Makoto Watanabe, Keiji Watanabe
  • Patent number: 8148049
    Abstract: A manufacturing method of an ink jet recording head includes steps of forming a liquid flow path mold material of a soluble resin on a substrate on which an energy generating element is formed, the energy generating element being configured to generate energy for use in discharging ink; forming a coating resin layer of a negative photosensitive resin on the substrate on which the mold material is formed; exposing and developing the coating resin layer to form an ink discharge port in the coating resin layer; and dissolving and removing the mold material to form a liquid flow path. During the exposing of the coating resin layer, a total amount of exposure energy per unit area applied to an exposure region other than a region of the coating resin layer positioned above the mold material is greater than that of exposure energy per unit area applied to the region of the coating resin layer positioned above the mold material.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: April 3, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroyuki Murayama, Junichi Kobayashi, Yoshinori Tagawa, Kenji Fujii, Hideo Tamura, Taichi Yonemoto, Keiji Watanabe
  • Patent number: 8091233
    Abstract: A method of manufacturing a liquid discharge head including a plurality of passages on a substrate, the passages communicating with a plurality of discharge ports configured to discharge liquid. The method includes the step of forming first, second, third, and fourth members, the first member having a shape of one passage, the second member having a shape of another member, the third member being formed near the first member, the fourth member being formed near the second member, the first to fourth members being formed on a surface of the substrate. The method also includes coating the substrate with a cover layer covering the first to fourth members, removing the first member to form the one passage, and removing the second member to form the another passage.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: January 10, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Taichi Yonemoto, Junichi Kobayashi, Yoshinori Tagawa, Hideo Tamura, Hiroyuki Murayama, Kenji Fujii, Keiji Watanabe
  • Patent number: 8047632
    Abstract: An ink jet recording head includes an ejection outlet for ejecting ink; an energy generating element, provided on a silicon substrate, for generating energy for ejecting the ink from the ejection outlet; an ink flow passage, provided correspondingly to the energy generating element, communicating with the ejection outlet; a through hole passing through the silicon substrate; and an ink supply port for supplying the ink supplied into the through hole to the ink flow passage. The ink supply port is formed with an extended member which contacts a bottom of a flow passage wall constituting the ink flow passage and extends into an opening of the through hole.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: November 1, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Fujii, Yoshinori Tagawa, Hiroyuki Murayama, Taichi Yonemoto, Mitsunori Toshishige, Keiji Watanabe
  • Patent number: 8037603
    Abstract: An ink jet head producing method includes forming a first flow path forming member in a portion constituting a flow path side wall, which constitutes at least a partitioning portion between flow paths on a substrate; forming a pattern as a mold for the flow path, the pattern being formed over the substrate and a portion of the first flow path forming member; forming a second flow path forming member on the first flow path forming member and the pattern, the second flow path forming member being formed of a material corresponding to the first flow path forming member; forming the discharge port in the second flow path forming member; and forming the flow path by removing the pattern.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: October 18, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Fujii, Junichi Kobayashi, Yoshinori Tagawa, Hideo Tamura, Hiroyuki Murayama, Keiji Watanabe, Taichi Yonemoto, Isamu Horiuchi, Aya Yoshihira, Masamichi Yoshinari, Jun Kawai, Tamaki Sato