Patents by Inventor Kishio Yokouchi

Kishio Yokouchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4761325
    Abstract: A method for producing a multilayer ceramic circuit board including the steps of forming a multilayer structure consisting of patterns of copper-based paste and glass-ceramic layers, the glass-ceramic layers consisting of a mixture of 10 percent to 75 percent by weight of .alpha.-alumina, 20 percent to 60 percent by weight of crystallizable or noncrystallizable glass which can be sintered at a temperature lower than the melting point of copper, and 5 percent to 70 percent by weight of quartz glass, based on the total weight of the glass-ceramic, blended with a binder containing a thermally depolymerizable resin; prefiring the multilayer structure in an inert atmosphere containing water vapor, the partial pressure of which is 0.005 to 0.3 atmosphere, at a temperature where the thermally depolymerizable resin is eliminated; and firing the multilayer structure in an inert atmosphere containing no water vapor at a temperature below the melting point of copper so as to sinter the glass-ceramic.
    Type: Grant
    Filed: August 2, 1985
    Date of Patent: August 2, 1988
    Assignee: Fujitsu Limited
    Inventors: Kazuaki Kurihara, Nobuo Kamehara, Hiromitsu Yokoyama, Hiromi Ogawa, Kishio Yokouchi, Yoshihiko Imanaka, Koichi Niwa
  • Patent number: 4704658
    Abstract: An evaporation cooling module for cooling plural semiconductor chips bonded on circuit boards immersed in a coolant within the module employs immersed heat exchangers associated with bubble traps which trap gaseous bubbles of evaporated coolant and maintain same in contact with the heat exchanger for improved reliquification efficiency. Bubble guides, which may be mounted to the circuit boards intermediate vertically spaced rows of semiconductor chips, guide gaseous bubbles of the evaporated coolant to the bubble trap, producing local convection coolant currents affording increased reliquification efficiency by released gases and improved temperature uniformity of the plural semiconductor chips. Use of immersed heat exchangers avoids decrease in reliquification efficiency since isolated therefrom. Bubble traps of predetermined porosity permit preferential separation of gaseous bubbles of the evaporated coolant and the undesired released gases.
    Type: Grant
    Filed: April 30, 1986
    Date of Patent: November 3, 1987
    Assignee: Fujitsu Limited
    Inventors: Kishio Yokouchi, Yuichi Suzuki, Koichi Niwa
  • Patent number: 4642148
    Abstract: A method for producing a multilayer ceramic circuit board including the steps of forming a multilayer structure consisting of patterns of copper-based paste and glass-ceramic layers, the glass-ceramic layers consisting of a mixture of 10 percent to 75 percent by weight of .alpha.-alumina, 20 percent to 60 percent by weight of crystallizable or noncrystallizable glass which can be sintered at a temperature lower than the melting point of copper, and 5 percent to 70 percent by weight of quartz glass, based on the total weight of the glass-ceramic, blended with a binder containing a thermally depolymerizable resin; prefiring the multilayer structure in an inert atmosphere containing water vapor, the partial pressure of which is 0.005 to 0.3 atmosphere, at a temperature where the thermally depolymerizable resin is eliminated; and firing the multilayer structure in an inert atmosphere containing no water vapor at a temperature below the melting point of copper so as to sinter the glass-ceramic.
    Type: Grant
    Filed: May 28, 1985
    Date of Patent: February 10, 1987
    Assignee: Fujitsu Limited
    Inventors: Kazuaki Kurihara, Nobuo Kamehara, Hiromitsu Yokoyama, Hiromi Ogawa, Kishio Yokouchi, Yoshihiko Imanaka, Koichi Niwa
  • Patent number: 4346516
    Abstract: A method of forming a ceramic circuit substrate allowing mounting of high integration density semiconductor elements. The method provides a multilayered ceramic circuit substrate having via holes formed with high accuracy and high integration density wiring patterns by forming metallic conductive balls to connect the conductive wiring patterns of upper and lower layers; a ball arranging plate having many holes placing on a green sheet uniformly in close contact; filling the holes of the plate with the embedding the conductive balls by pressure into the green sheet; and thereafter baking the green sheet individually or in a stacked layered arrangement.
    Type: Grant
    Filed: April 8, 1981
    Date of Patent: August 31, 1982
    Assignee: Fujitsu Limited
    Inventors: Kishio Yokouchi, Hiromi Ogawa, Hiromitsu Yokoyama, Nobuo Kamehara, Koichi Niwa, Kyohei Murakawa