Patents by Inventor Kiyoshi Yoneda

Kiyoshi Yoneda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6951495
    Abstract: A display apparatus includes display pixels each having a thin film transistor and an EL element formed successively forming over a substrate. The EL element has a cathode electrode connected to the source of the thin film transistor and an anode electrode, and is driven by the thin film transistor. The EL element externally emits light from the reverse side of the substrate. For example, when the cathode electrode is formed the comblike, meshlike, or gridlike pattern on the luminous layer, the light is emitted through the slits of the cathode pattern. The display apparatus is provided that can improve the aperture ratio of a display pixel and can increase the degree of freedom in deciding the size and the drive capability of a TFT element which drives an EL element.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: October 4, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Kiyoshi Yoneda
  • Patent number: 6924508
    Abstract: A first moisture blocking layer formed of a silicon type nitride film such as SiNx or the like is formed over the entire surface so as to cover a drain electrode and a source electrode of a TFT. On the first moisture blocking layer, a first planarization film formed of an organic material is provided. On the first planarization film, a second moisture blocking layer formed of SiNx or the like is provided. In the peripheral region, the second moisture blocking layer extends down on the first moisture blocking layer and is connected with the first moisture blocking layer. Also, a sealing glass is bonded to the second moisture blocking layer using the sealing member. By enclosing the first planarization film by the first moisture blocking layer and the second moisture blocking layer, intrusion of external moisture can be effectively prevented.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: August 2, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kiyoshi Yoneda, Ryuji Nishikawa
  • Publication number: 20050140277
    Abstract: A display device having a plurality of pixels and which realizes a color display using emitted light of at least two wavelengths, wherein each pixel has a microresonator structure formed between a lower reflective film formed on a side near a substrate and an upper reflective film formed above the lower reflective film with an organic light emitting element layer therebetween. The lower reflective film is made of a metal thin film and a conductive resonator spacer layer which functions as a first electrode is provided between the lower reflective film and the organic light emitting element layer. A thickness of the conductive resonator spacer layer is changed by changing a number of layers or a number of remaining layers of a transparent conductive metal oxide layer made of ITO and a light transmissive layer 210 made of SiNx or the like corresponding to the light emission wavelength.
    Type: Application
    Filed: December 22, 2004
    Publication date: June 30, 2005
    Inventors: Koji Suzuki, Ryuji Nishikawa, Kiyoshi Yoneda
  • Publication number: 20050068272
    Abstract: A pixel selecting TFT is made of a polysilicon TFT, in which a gate insulating layer is formed on an active layer made of a polysilicon layer formed on a transparent insulating substrate made of a glass substrate or the like, and two gates and extend from a gate signal line. A driving TFT is made of an amorphous silicon TFT, in which a gate insulating layer is formed on an active layer made of an amorphous silicon layer formed on the transparent insulating substrate, and a gate made of a Cr layer, a Mo layer or the like is formed on the gate insulating layer.
    Type: Application
    Filed: October 1, 2003
    Publication date: March 31, 2005
    Applicant: Sanyo Electric Co., Ltd.
    Inventor: Kiyoshi Yoneda
  • Publication number: 20050062047
    Abstract: A device has a first transistor and a second transistor wherein a channel length direction of the first transistor extends along a first direction and a channel length direction of the second transistor extends along a second direction intersecting the first direction, and the second transistor is formed on a same substrate as the first transistor. A first channel region and a second channel region are formed in semiconductor layers which are simultaneously formed and a mobility of the semiconductor film has an anisotropy in the first and second directions. With this structure, transistors having different mobilities can be obtained while using the semiconductor films formed on the same substrate and from a same material. For example, it is possible to form a transistor in which a high resistance is required using a semiconductor layer of the same characteristics as that in a transistor in which a high speed operation is desired, on the same substrate and with a minimum area.
    Type: Application
    Filed: September 21, 2004
    Publication date: March 24, 2005
    Inventors: Ryuji Nishikawa, Kazuhiro Imao, Ken Wakita, Kiyoshi Yoneda
  • Publication number: 20050042809
    Abstract: In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.
    Type: Application
    Filed: September 21, 2004
    Publication date: February 24, 2005
    Inventors: Nobuhiko Oda, Toshifumi Yamaji, Shiro Nakanishi, Yoshihiro Morimoto, Kiyoshi Yoneda
  • Patent number: 6858512
    Abstract: An a-Si film (12) formed on an insulating substrate (10) is irradiated with a laser so that the a-Si film (12) is fused and recrystallized to form a p-Si film (13). Projections (100) generated on the p-Si film (13) at this stage are eliminated by irradiation of ion beams at the incident angle of 60° to 90° using an ion milling method to planarize the surface of the p-Si film (13), thereby creating sufficient insulation between the p-Si film (13) and gate electrodes (15).
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: February 22, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoshihiro Morimoto, Kiyoshi Yoneda
  • Publication number: 20050035932
    Abstract: This invention provides an organic EL display device automatically correcting light emission intensity of a display portion in accordance with intensity of external light, in which the number of components is reduced and sensitivity in detection of an external light sensor is improved. An organic EL element of top emission type, a driving TFT for driving the organic EL element, which is formed of a TFT of top gate type, and an external light sensor formed of a TFT of bottom gate type are integrally formed on a same glass substrate. Since the external light sensor is formed of a TFT of bottom gate type, external light is not blocked by a gate electrode, thereby improving sensitivity in detection of the external light.
    Type: Application
    Filed: June 24, 2004
    Publication date: February 17, 2005
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Ryuji Nishikawa, Kiyoshi Yoneda
  • Publication number: 20050035348
    Abstract: In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper (55) is removed. The ion stopper (55) does not remain in the interlayer insulating film (8) lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper (55), and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer (4). The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.
    Type: Application
    Filed: September 20, 2004
    Publication date: February 17, 2005
    Inventors: Nobuhiko Oda, Toshifumi Yamaji, Shiro Nakanishi, Yoshihiro Morimoto, Kiyoshi Yoneda
  • Patent number: 6850005
    Abstract: An inter-layer insulating film and a gate insulating film which are positioned on the optical path of light from an organic EL element to be externally emitted, for example, located under a transparent electrode, are removed. Because SiO2 films having a refractive index which differs significantly from refractive indexes of other films are used for these films, there was a problem of light attenuation in these layers. Such light attenuation can be reduced by removing these layers located in the region through which light from the organic EL element passes.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: February 1, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kiyoshi Yoneda, Ryuji Nishikawa, Koji Suzuki, Shinji Ichikawa
  • Publication number: 20050014316
    Abstract: A method of fabricating a thin film transistor by setting the temperature of a heat treatment for crystallizing an active layer which is formed on a substrate at a level not deforming the substrate and activating an impurity layer in a heat treatment method different from that employed for the heat treatment, and a semiconductor device prepared by forming a heat absorption film, a semiconductor film, a gate insulating film, and a gate electrode on a substrate, the heat absorption film being provided within a region substantially corresponding to the semiconductor film.
    Type: Application
    Filed: August 13, 2004
    Publication date: January 20, 2005
    Inventors: Kiichi Hirano, Naoya Sotani, Toshifumi Yamaji, Yoshihiro Morimoto, Kiyoshi Yoneda
  • Publication number: 20040222736
    Abstract: The invention is directed to an increase of luminous efficiency of a white organic EL element. A white emissive layer of an organic EL element is formed by laminating a blue emissive layer and a yellow emissive layer. The blue emissive layer emitting blue light having a short wavelength is formed on a side nearer to the anode layer, and the yellow emissive layer emitting yellow light having a longer wavelength than the blue emissive layer is disposed on the blue emissive layer. Under this configuration, the blue light emitted from the blue emissive layer reaches the color filter layer without penetrating through the yellow emissive layer. On the other hand, the yellow light emitted from the yellow emissive layer penetrates through the blue emissive layer. The yellow light has a longer wavelength than the blue light, an absorption amount of the yellow light becomes relatively small. An absorption amount of the blue light also reduces, so that the luminous efficiency increases.
    Type: Application
    Filed: March 2, 2004
    Publication date: November 11, 2004
    Applicant: Sanyo Electric Co., Ltd.
    Inventor: Kiyoshi Yoneda
  • Patent number: 6815272
    Abstract: In a bottom gate-type thin-film transistor manufacturing method, after ion doping, an ion stopper is removed. The ion stopper does not remain in the interlayer insulating film lying immediately above the gate electrode. The thin-film transistor has such a structure that no ion stopper, and the interlayer insulating layer is in direct contact with at least the channel region of the semiconductor layer. The impurity concentration in the vicinity of the interface between the interlayer insulating film and the semiconductor layer 4 is 1018 atoms/cc or less. This structure can prevent the back channel phenomenon and reduce variations in characteristic resulting from variations in manufacturing.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: November 9, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Nobuhiko Oda, Toshifumi Yamaji, Shiro Nakanishi, Yoshihiro Morimoto, Kiyoshi Yoneda
  • Publication number: 20040217695
    Abstract: An (inner) second planarization film which is an insulating film in the form of a frame and an (outer) second planarization film which has a high profile and pillar shape are formed so as to cover the periphery of a pixel electrode. Subsequently, when an organic emissive layer is subjected to mask evaporation, only a region wherein the (outer) second planarization film is provided comes into contact with the mask. Accordingly, the occurrence of scraping of the mask or dislodging of dust can be reduced, and any resulting scrapings or dust are trapped between the (outer) second planarization film and the (inner) second planarization film.
    Type: Application
    Filed: July 24, 2003
    Publication date: November 4, 2004
    Inventors: Kiyoshi Yoneda, Ryuji Nishikawa
  • Publication number: 20040217355
    Abstract: The invention prevents emitting of a bit of light from an organic EL element and affecting of a display. A gate insulating layer is formed extending on an active layer made of a polysilicon layer which is formed on a transparent insulating substrate made of a glass substrate. A gate extends over the gate insulating layer. An active layer is formed with a source/drain having an LDD structure. A source is formed of a P+ layer and a P− layer which are in contact with each other. The P+ layer is a high concentration layer of boron as an impurity with concentration of about 1×1020/cc. The P− layer is a low concentration layer containing boron as an impurity with concentration of about 1×1018/cc, and formed extending in a direction between the P+ layer and the gate. A drain is also formed of a P+ layer and a P− layer which are in contact with each other.
    Type: Application
    Filed: March 2, 2004
    Publication date: November 4, 2004
    Applicant: Sanyo Electric Co., Ltd.
    Inventor: Kiyoshi Yoneda
  • Publication number: 20040217714
    Abstract: The invention prevents an uneven display on an organic EL display panel by reducing characteristic variation of a driving transistor among pixels. A gate signal line for supplying a gate signal and a drain signal line for supplying a display signal are crossing each other. Four split driving TFTs of P-channel type are provided in a pixel, and drains of the driving TFTs are connected with anodes of split organic EL elements, respectively. A common gate of the driving TFTs is connected with a pixel selecting TFT.
    Type: Application
    Filed: March 2, 2004
    Publication date: November 4, 2004
    Applicant: Sanyo Electric Co., Ltd.
    Inventor: Kiyoshi Yoneda
  • Patent number: 6812912
    Abstract: An active matrix display device employing a top gate type TFT structure has a storage capacitor Csc and a liquid crystal capacitor Clc in each pixel of a pixel section, a first electrode of the storage capacitor Csc served by a p-Si active layer of the TFT, and a second electrode formed to at least partly overlap the active layer, with an insulating layer between the active layer and the second electrode below it. When a driver section is to be built in, the driver section TFT is the same top gate type as the pixel section TFT, and an active layer is made of the same material as the active layer and has a conductive layer which is made of the same material as the second electrode with the insulating layer held between the active layer and the conductive layer below it. The pixel section can form the storage capacitor while preventing lowering of the aperture ratio.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: November 2, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasushi Miyajima, Ryoichi Yokoyama, Tsutomu Yamada, Kiyoshi Yoneda
  • Publication number: 20040211956
    Abstract: A hole injecting electrode composed of ITO is formed on a glass substrate. On the hole injecting electrode, a hole injecting layer composed of CuPc (copper phthalocyanine), a plasma thin film of CFx formed by plasma CVD, a hole transporting layer of NPB, and a light emitting layer are formed in the order. On the light emitting layer, an electron transporting layer is formed, and an electron injecting electrode is formed thereon.
    Type: Application
    Filed: September 24, 2003
    Publication date: October 28, 2004
    Inventors: Hiroshi Kanno, Kiyoshi Yoneda, Kazuki Nishimura, Yuji Hamada
  • Publication number: 20040183074
    Abstract: In a fabrication process of a semiconductor device for use in a TFT liquid crystal display system, before the start of crystallizing amorphous silicon (a-Si), dehydrogenation annealing is carried out to not only decrease the density of hydrogen in the p-Si film (13) to 5×1020 atoms/cm3 at most but also to prevent crystallization of the a-Si film (13) being obstructed due to possible excessive hydrogen remaining in the film. With the p-Si film (13) covered with an interlayer insulation film (15) in the form of a plasma nitride film, annealing is then carried out in nitrogen atmosphere at a temperature of 350° C. to 400° C. for one to three hours, more preferably 400° C. for two hours. The result is that hydrogen atoms in the p-Si film (13) efficiently terminate dangling bonds of the film and hence do not become excessive, thus improving the electrical characteristics of the semiconductor device.
    Type: Application
    Filed: April 5, 2004
    Publication date: September 23, 2004
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventors: Yushi Jinno, Shiro Nakanishi, Kyoko Hirai, Tsutomu Yamada, Yoshihiro Morimoto, Kiyoshi Yoneda
  • Patent number: 6790714
    Abstract: A method of fabricating a thin film transistor by setting the temperature of a heat treatment for crystallizing an active layer which is formed on a substrate at a level not deforming the substrate and activating an impurity layer in a heat treatment method different from that employed for the heat treatment, and a semiconductor device prepared by forming a heat absorption film, a semiconductor film, a gate insulating film, and a gate electrode on a substrate, the heat absorption film being provided within a region substantially corresponding to the semiconductor film.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: September 14, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kiichi Hirano, Naoya Sotani, Toshifumi Yamaji, Yoshihiro Morimoto, Kiyoshi Yoneda