Abstract: A compression device includes an analyzer circuit, a control circuit, a compressor circuit, and a selector circuit. The analyzer circuit is configured to analyze first data that is input thereto and generate one or more parameter values regarding data compression and/or decompression. The control circuit is configured to generate at least one compression mode information indicating whether or not compression is to be performed, based on the one or more parameter values. The compressor circuit is configured to compress the first data into second data according to the compression mode information. The selector circuit is configured to output the first data if not compressed or the second data if the first data is compressed, together with the compression mode information.

Abstract: According to one embodiment, a memory system includes a frequency value update unit, a first intra-group rearranging unit, a second intra-group rearranging unit, and a routing unit. The frequency value update unit adds a first value to each of one or more first frequency values that are associated with one or more first symbols, respectively, in one or more entries in a table. The first intra-group rearranging unit rearranges first entries, which belong to a first group, using frequency values in the first entries. The second intra-group rearranging unit rearranges second entries, which belong to a second group lower than the first group, using frequency values. The routing unit rearranges at least one of the first entries and at least one of the second entries.

Abstract: A memory system including a history buffer, a hash calculator, a read pointer table, a history buffer writing circuit, a read pointer writing circuit, a read pointer reading circuit, a history buffer reading circuit, a matching circuit replacing the input data string with a reference information referring the matching candidate data string in the case where at least a part of the input data string and a part of the matching candidate data string match. Reading of the read pointer by the read pointer reading circuit and reading of the stored input data string by the history buffer reading circuit are executed after writing of the read pointer by the read pointer writing circuit and writing of the input data string by the history buffer writing circuit are finished.

Abstract: According to one embodiment, a memory system includes a frequency value update unit, a first intra-group rearranging unit, a second intra-group rearranging unit, and a routing unit. The frequency value update unit adds a first value to each of one or more first frequency values that are associated with one or more first symbols, respectively, in one or more entries in a table. The first intra-group rearranging unit rearranges first entries, which belong to a first group, using frequency values in the first entries. The second intra-group rearranging unit rearranges second entries, which belong to a second group lower than the first group, using frequency values. The routing unit rearranges at least one of the first entries and at least one of the second entries.

Abstract: According to one embodiment, a memory system includes a compressor configured to output second data obtained by compressing input first data and a non-volatile memory to which third data based on the second data output from the compressor is written. The compressor includes a dictionary coding unit configured to perform dictionary coding on the first data, an entropy coding unit configured to perform entropy coding on the result of the dictionary coding, a first calculation unit configured to calculate compression efficiencies of the dictionary coding and the entropy coding, and a first control unit configured to control an operation of at least one of the dictionary coding unit and the entropy coding unit based on the compression efficiencies and a power reduction level.

Abstract: According to one embodiment, a buffer stores first hash values and first complementary data. A first conversion unit converts consecutive characters in a second character string into second hash values and second complementary data. A search unit searches for consecutive first hash values from the buffer, and output a pointer. A selection unit selects consecutive first hash values and pieces of first complementary data from the buffer. A second conversion unit converts the consecutive first hash values into a third character string using the pieces of first complementary data. A comparison unit compares the second character string with the third character string to acquire a matching length. An output unit output the matching length with the pointer.

Abstract: A memory system including a storage device and a memory controller controlling the storage device and decoding an encoded data. The memory controller including: a history buffer storing a decoded data string; a history buffer read controller executing a read request to the history buffer; a decode executing section generating a first shaped data string based on the decoded data string read from the history buffer, generating a second shaped data string by referring the first shaped data string before the first shaped data string being written back to the history buffer in response to the read request, and generating a decoded result using the first shaped data string and the second shaped data string.

Abstract: According to one embodiment, a dividing circuit divides a first bit string into second bit strings and outputs the divided second bit strings. The dividing circuit includes first, second, and third blocks. The first block executes first operation for each bit of a third bit string in the first bit string. The first operation is to calculate a head bit of a succeeding symbol when one bit is assumed to be a head of one symbol. The second block executes second operation for each bit of the third bit string for a set number of times. The second operation is to overwrite boundary information associated with one bit with boundary information associated with a bit indicated by the boundary information. The third block divides the third bit string immediately before a second bit indicated by boundary information associated with a first bit of the third bit string.

Abstract: According to one embodiment, a compression device includes a first storage unit, a second storage unit, a calculation unit, and a comparison unit. The first storage unit stores addresses associated with hash values, respectively. The second storage unit includes storage areas specified by the addresses, respectively. The calculation unit determines a hash function to be used for first data in accordance with at least a part of the first data, and calculates a hash value using the hash function and at least a part of second data included in the first data. The comparison unit acquires third data from a storage area in the second storage unit specified by a first address, and compares the second data with the third data. The first address is stored in the first storage unit and is associated with the hash value.

Abstract: A compression device includes a dictionary based encoder, a second buffer, a comparator, and a compression data generator. The dictionary based encoder searches for second data at least partially matching first data from a first buffer, and acquires a first match position indicating a position of the second data in the first buffer and a match length indicating a matched length of the first and second data. The second buffer stores the previously acquired second match position with an index. The compression data generator generates first compressed data that includes the index assigned to the second match position in the second buffer and the match length when the first match position matches the second match position in the second buffer.

Abstract: A memory system includes a storage device and a memory controller. The memory controller includes an encoder and a decoder. The encoder includes a first code table updating section configured to update the encoding code table and an encoding flow controlling section configured to control input to the first code table updating section by using a first data amount indicating a data amount of the input symbol. The first data amount is calculated based on the input symbol. The decoder includes a second code table updating section configured to update the decoding code table and a decoding flow controlling section configured to control input to the second code table updating section by using a second data amount indicating a data amount of the output symbol. The second data amount is calculated based on the output symbol in the same way as the calculation of the first data amount.

Abstract: A memory system including a history buffer, a hash calculator, a read pointer table, a history buffer writing circuit, a read pointer writing circuit, a read pointer reading circuit, a history buffer reading circuit, a matching circuit replacing the input data string with a reference information referring the matching candidate data string in the case where at least a part of the input data string and a part of the matching candidate data string match. Reading of the read pointer by the read pointer reading circuit and reading of the stored input data string by the history buffer reading circuit are executed after writing of the read pointer by the read pointer writing circuit and writing of the input data string by the history buffer writing circuit are finished.

Abstract: A memory system including a storage device and a memory controller controlling the storage device and decoding an encoded data. The memory controller including: a history buffer storing a decoded data string; a history buffer read controller executing a read request to the history buffer; a decode executing section generating a first shaped data string based on the decoded data string read from the history buffer, generating a second shaped data string by refferring the first shaped data string before the first shaped data string being written back to the history buffer in response to the read request, and generating a decoded result using the first shaped data string and the second shaped data string.

Abstract: According to one embodiment, a memory system includes a frequency value update unit, a first intra-group rearranging unit, a second intra-group rearranging unit, and a routing unit. The frequency value update unit adds a first value to each of one or more first frequency values that are associated with one or more first symbols, respectively, in one or more entries in a table. The first intra-group rearranging unit rearranges first entries, which belong to a first group, using frequency values in the first entries. The second intra-group rearranging unit rearranges second entries, which belong to a second group lower than the first group, using frequency values. The routing unit rearranges at least one of the first entries and at least one of the second entries.

Abstract: According to one embodiment, a compression device includes a dictionary based encoder, a second buffer, a comparator, and a compression data generator. The dictionary based encoder searches for second data at least partially matching first data from a first buffer, and acquires a first match position indicating a position of the second data in the first buffer and a match length indicating a matched length of the first and second data. The second buffer stores the previously acquired second match position with an index. The compression data generator generates first compressed data that includes the index assigned to the second match position in the second buffer and the match length when the first match position matches the second match position in the second buffer.

Abstract: According to one embodiment, a dividing circuit divides a first bit string into second bit strings and outputs the divided second bit strings. The dividing circuit includes first, second, and third blocks. The first block executes first operation for each bit of a third bit string in the first bit string. The first operation is to calculate a head bit of a succeeding symbol when one bit is assumed to be a head of one symbol. The second block executes second operation for each bit of the third bit string for a set number of times. The second operation is to overwrite boundary information associated with one bit with boundary information associated with a bit indicated by the boundary information. The third block divides the third bit string immediately before a second bit indicated by boundary information associated with a first bit of the third bit string.

Abstract: A memory system includes a first memory that is nonvolatile, a second memory that is volatile, and a memory controller. The memory controller is configured to store first information in the second memory. The first information includes management information. The memory controller is further configured to compress the first information. The compressed first information is second information. The memory controller is configured to store the second information in the first memory.

Abstract: A memory device includes a non-volatile first memory in which a conversion table is stored, a second memory, and a controller configured to control the first memory and the second memory, and including a cache control circuit. The cache control circuit is configured to set up a circular buffer with a write pointer, and store portions of the conversion table in the circular buffer. Each of the portions of the conversion table contain a plurality of logical address to physical address mappings, and each of the portions have a corresponding entry in a management table stored in the second memory, and each entry of the management table includes an address field for storing an address of the circular buffer used in locating the corresponding portion of the conversion table and a size field for storing a size of the corresponding portion.

Abstract: A memory device includes a non-volatile first memory in which a conversion table is stored, a second memory, and a controller configured to control the first memory and the second memory, and including a cache control circuit. The cache control circuit is configured to set up a circular buffer with a write pointer, and store portions of the conversion table in the circular buffer. Each of the portions of the conversion table contain a plurality of logical address to physical address mappings, and each of the portions have a corresponding entry in a management table stored in the second memory, and each entry of the management table includes an address field for storing an address of the circular buffer used in locating the corresponding portion of the conversion table and a size field for storing a size of the corresponding portion.

Abstract: According to one embodiment, a memory system includes an error mitigation encoder that executes error mitigation coding on write data to be stored in a processing target page of a non-volatile memory, a memory interface that writes the write data which has undergone the error mitigation coding in the processing target page of the non-volatile memory and reads the write data which has undergone the error mitigation coding from the processing target page as read data, an error mitigation decoder that performs error mitigation decoding on the read data read from the processing target page of the non-volatile memory, and an error mitigation coding rate deciding unit that decides an error mitigation coding rate of the error mitigation encoder and the error mitigation decoder on the basis of at least one of information indicating the processing target page and information indicating a device characteristic of the processing target page.