Abstract: According to the embodiments, a controller includes an arbiter, a command fetch unit, and a processing unit. The arbiter executes a retrieval process. The retrieval process is a process of selecting a queue, to which a command is issued, out of plural queues by retrieval according to a round robin method. The command fetch unit fetches a command from the selected queue. The processing unit executes a process according to the fetched command to a memory chip. The arbiter manages a retrieval position. When a new command is issued to any one of the plural queues in an empty state in which there is no queue to which a command is issued, the arbiter has the retrieval position jump to the queue to which the new command is issued.

Abstract: According to one embodiment, a memory controller includes: a first flash encoding unit that performs flash encoding on user data according to a first scheme to generate user data flash codes; an encoding unit that performs an error correction encoding process on the user data flash codes to generate parities; a second flash encoding unit that performs flash encoding on the parities according to a second scheme to generate parity flash codes; and a memory I/F that writes the user data flash codes and the parity flash codes to the nonvolatile memory.

Abstract: A memory system includes a first nonvolatile memory, a second nonvolatile memory with a longer access latency than the first nonvolatile memory, a first error correction unit, a second error correction unit, and an interface. The first nonvolatile memory stores first data and a first error correction code generated for the first data. The second nonvolatile memory stores a second error correction code which is generated for the first data with a higher correction ability than that of the first error correction code. The first error correction unit performs error correction on the first data by using the first error correction code. The second error correction unit performs error correction on the first data by using the second error correction code. The interface transmits the first data after the error correction to a host.

Abstract: According to one embodiment, a memory system includes a plurality of nonvolatile memories, an address converter, a plurality of channel controllers, and a controller. The plurality of nonvolatile memories is connected to respective channels. The address converter converts a logical address of a read request into a physical address of the nonvolatile memories. Each of the channel controllers is provided to each of the channels. Each of the channel controllers has a plurality of queues, each queues stores at least two read request. The controller selects a queue which stores no read request, and transfers the read request to the selected queue.

Abstract: According to one embodiment, a memory system includes a first memory, a second memory, and a control unit. The first memory includes a volatile first register retaining a first operation parameter. The control unit performs a first operation of retaining the first operation parameter in the second memory. Then, the control unit turns OFF the first memory while retaining the first operation parameter in the second memory when an operation mode is switched from a first mode to a power saving second mode. Then, the control unit performs a second operation of turning on the first memory, and transferring the first operation parameter retained in the second memory to the first register when the operation mode is switched from the second mode to the first mode.

Abstract: A memory circuit according to an embodiment includes: a plurality of memory cells each having one pair of first and second nonvolatile memory circuits, each of the first and second nonvolatile memory circuits in each memory cell being capable of making a transition between a high resistance state and a low resistance state, and in a state in which one memory cell in the plurality of memory cells has information stored therein, one of the first and second nonvolatile memory circuits in the one memory cell being in a high resistance state whereas the other being in a low resistance state.

Abstract: According to one embodiment, a storage device comprises a first storage unit having blocks, each including pages, a second storage unit having a free block list, and a free page list, and a control unit. In write data in units of blocks, the control unit generates compressed data blocks by compressing the data in units of blocks, writes the compressed data blocks to the blocks which can be written in accordance with the information held in the free block list, holds, in the free page list, the information about pages existing in free areas which are provided in the blocks holding compressed data blocks and which holds no compressed data blocks. In write data in units of pages, the control unit writes the data in units of pages to pages existing in the free areas, in accordance with the information held in the free page list.

Abstract: According to one embodiment, a storage device comprises a first storage unit having blocks, each including pages, a second storage unit having a free block list, and a free page list, and a control unit. In write data in units of blocks, the control unit generates compressed data blocks by compressing the data in units of blocks, writes the compressed data blocks to the blocks which can be written in accordance with the information held in the free block list, holds, in the free page list, the information about pages existing in free areas which are provided in the blocks holding compressed data blocks and which holds no compressed data blocks. In write data in units of pages, the control unit writes the data in units of pages to pages existing in the free areas, in accordance with the information held in the free page list.

Abstract: According to one embodiment, a semiconductor storage device includes a cell array, a controller, and a voltage generator. The cell array includes cells. Each of the cells holds data “0” or “1”. The controller counts the number of times N of sequentially writing the data into the cells. The controller transfers a write voltage and a read voltage. The write voltage and the read voltage are variable according to the number of times N. The voltage generator generates the write voltage and the read voltage. When the N-th (?2) write request is issued to the cell, the controller causes the voltage generator to generate the read voltage corresponding to an (N?1)th time. The controller causes the voltage generator to generate the write voltage which changes a threshold voltage of the cell. When the cell has reached a prescribed value, the controller erases the data held in the cell.

Abstract: A semiconductor integrated circuit according to an aspect of the invention includes a plurality of master devices which issue data transfer requests, at least one slave device which performs data transfer in accordance with the data transfer requests, and a network which arbitrates the plurality of data transfer requests respectively issued from the plurality of master devices, and informs the slave device of the arbitration result, thereby performing data transfer between the master devices and the slave device, wherein when issuing the data transfer request, the master device informs the network of a period which extends from the issuance of the data transfer request to the start of the data transfer.

Abstract: A semiconductor integrated circuit including a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network, to a second point of the second clock distribution network, and a second phase synchronizer which provides a second output signal obtained by making the phase of the clock signal at a third point of the first clock distribution network coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of the first clock distribution network.

Abstract: A semiconductor integrated circuit including a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network, to a second point of the first clock distribution network, and a second phase synchronizer which provides a second output signal obtained by making the phase of the reference clock signal coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of the second clock distribution network.

Abstract: A semiconductor integrated circuit according to an aspect of the invention includes a plurality of master devices which issue data transfer requests, at least one slave device which performs data transfer in accordance with the data transfer requests, and a network which arbitrates the plurality of data transfer requests respectively issued from the plurality of master devices, and informs the slave device of the arbitration result, thereby performing data transfer between the master devices and the slave device, wherein when issuing the data transfer request, the master device informs the network of a period which extends from the issuance of the data transfer request to the start of the data transfer.

Abstract: A data transfer circuit includes a first transfer circuit receiving the first transfer signal, a second transfer circuit receiving the second transfer signal, a third transfer circuit receiving the first transfer signal and an inverted first transfer signal from the first transfer circuit and transferring the first transfer signal in response to a reply signal, a fourth transfer circuit receiving the second transfer signal and an inverted second transfer signal from the second transfer circuit and transferring the second transfer signal in response to the reply signal.

Abstract: A semiconductor integrated circuit including a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network, to a second point of the second clock distribution network, and a second phase synchronizer which provides a second output signal obtained by making the phase of the clock signal at a third point of the first clock distribution network coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of the first clock distribution network.

Abstract: A semiconductor integrated circuit including a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a first phase synchronizer which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at a first point of the first clock distribution network, to a second point of the first clock distribution network, and a second phase synchronizer which provides a second output signal obtained by making the phase of the reference clock signal coincident with a phase of a clock signal at a first point of the second clock distribution network, to a second point of the second clock distribution network.

Abstract: A circuit according to an embodiment of the present invention comprises a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region supplied with a second power supply voltage, and having a second clock distribution network, a PLL circuit which provides a first output signal obtained by making a phase of a reference clock signal for controlling a data input/output coincident with a phase of a clock signal at an end point of the first clock distribution network, to a start point of the first clock distribution network, and a PLL circuit which provides a second output signal obtained by making the phase of the reference clock signal coincident with a phase of a clock signal at an end point of the second clock distribution network, to a start point of the second clock distribution network.

Abstract: An aspect of the present invention provides a ferroelectric memory comprising a cell block having a plurality of unit cells connected in series, one end of the cell block being connected to a plate line and the other end of the cell block being connected to a bit line through a block selecting transistor, a sense amplifier connected to the bit line, and a block selector decoder which controls ON/OFF of the block selecting transistor. The timing for operating the sense amplifier and block selector decoder is changed corresponding to a position of a selected unit cell objective for data read of the plurality of unit cells.

Abstract: A semiconductor device includes an internal power supply, at least one semiconductor circuit block, a delay circuit, and a detecting circuit. The internal power supply outputs an initialization completion signal when initialized. The semiconductor circuit block operates on the basis of a voltage generated by the internal power supply. The delay circuit delays the initialization completion signal. The detecting circuit commands the semiconductor circuit block to start operations in response to the initialization completion signal delayed by the delay circuit and an externally input first input signal.

Abstract: A semiconductor device includes first, second, third and fourth resistor elements. The first to fourth resistor elements have first ends commonly connected to a first node, and operate in one of first and second operation modes which are switchable. The first and second resistor elements have second ends connected to a second node and a third node, respectively. The third and fourth resistor elements have second ends connected to a fourth node and a fifth node via a first switch and a second switch, respectively. The first and second switches are opened in the first operation mode, and are closed in the second operation mode.