Patents by Inventor Koji Yamakawa

Koji Yamakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8587043
    Abstract: According to one embodiment, a magnetoresistive random access memory includes a magnetoresistive element in a memory cell, the magnetoresistive element including a first metal magnetic layer, a second metal magnetic layer, and an insulation layer interposed between the first and second metal magnetic layers. An area of each of the first and second metal magnetic layers is smaller than an area of the insulation layer.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: November 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Koji Yamakawa, Daisuke Ikeno
  • Publication number: 20130220223
    Abstract: [Object] To provide a radical generator which can produce radicals at higher density. [Means for Solution] The radical generator includes a supply tube 10 made of SUS, a hollow cylindrical plasma-generating tube 11 which is connected to the supply tube 10 and which is made of pyrolytic boron nitride (PBN). A cylindrical CCP electrode 13 is disposed outside the plasma-generating tube 11. A coil 12 is provided so as to wind about the outer circumference of the plasma-generating tube at the downstream end of the CCP electrode 13. A parasitic-plasma-preventing tube 15 made of a ceramic material is inserted into an opening of the supply tube 10 at the connection site between the supply tube 10 and the plasma-generating tube 11.
    Type: Application
    Filed: August 24, 2011
    Publication date: August 29, 2013
    Applicants: KATAGIRI Engineering Co, Ltd., NU Eco Engineering Co. Ltd.
    Inventors: Masaru Hori, Hiroshi Amano, Hiroyuki Kano, Shoji Den, Koji Yamakawa
  • Patent number: 8410529
    Abstract: According to one embodiment, a semiconductor device, includes a magneto resistive element including a first magnetic layer, a first interface magnetic layer, a nonmagnetic layer, a second interface magnetic layer and a second magnetic layer as a stacked structure in order; and a metal layer including first metal atoms, second metal atoms and boron atoms, the metal layer being provided at least one region selected from under the first magnetic, between the first magnetic layer and the first interface magnetic layer, between the second interface magnetic layer and the second magnetic layer, and upper the second magnetic layer.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: April 2, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Ikeno, Koji Yamakawa, Katsuaki Natori, Yasuyuki Sonoda
  • Publication number: 20130056349
    Abstract: Provided are a sputtering target including a target main body 10 that has MgO as a main component and a thickness of 3 mm or smaller, and a method of manufacturing a magnetic memory using the sputtering target which improves an MR ratio.
    Type: Application
    Filed: August 31, 2012
    Publication date: March 7, 2013
    Inventors: Eiji KITAGAWA, Tadaomi DAIBOU, Kenji NOMA, Tadashi KAI, Koji YAMAKAWA, Toshihiko NAGASE, Katsuya NISHIYAMA, Koji UEDA, Daisuke WATANABE, Hiroaki YODA, Satoru SANO, Yoshihiro NISHIMURA, Takayuki WATANABE, Yuzo KATO, Akira UEKI
  • Publication number: 20130027697
    Abstract: The multi-micro hollow cathode light source has a cathode plate, an insulation plate, an anode plate, and metal pieces. The insulation plate is sandwiched by the cathode plate and the anode plate. The cathode plate is made of copper. The centers of the cathode plate, insulation plate, and anode plate, are provided with holes, respectively. The holes form a penetrating though-hole. Linear slots are disposed in the cathode plate continuously extending from the hole in a cross shape. Each slot penetrates the cathode plate. Four metal pieces made of materials different from one another are inserted and buried in the four slots.
    Type: Application
    Filed: February 8, 2011
    Publication date: January 31, 2013
    Inventors: Masaru Hori, Masafumi Ito, Takayuki Ohta, Hiroyuki Kano, Koji Yamakawa
  • Publication number: 20130001715
    Abstract: In accordance with an embodiment, a magnetoresistive element includes a lower electrode, a first magnetic layer on the lower electrode, a first interfacial magnetic layer on the first magnetic layer, a nonmagnetic layer on the first interfacial magnetic layer, a second interfacial magnetic layer on the nonmagnetic layer, a second magnetic layer on the second interfacial magnetic layer; and an upper electrode layer on the second magnetic layer. Either the first magnetic and interfacial magnetic layers or the second magnetic and interfacial magnetic layers constitute a storage layer. The other layers of the first magnetic and interfacial magnetic layers and the second magnetic and interfacial magnetic layers constitute a reference layer. The lower electrode includes an alloy layer or mixture layer of a precious metal and a transition element or a rare earth element, or comprises a conductive oxide layer.
    Type: Application
    Filed: March 20, 2012
    Publication date: January 3, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji YAMAKAWA, Katsuaki NATORI, Daisuke IKENO
  • Publication number: 20130001716
    Abstract: In accordance with an embodiment, a magnetoresistive element includes a lower electrode, a first magnetic layer on the lower electrode, a first diffusion prevention layer on the first magnetic layer, a first interfacial magnetic layer on the first metal layer, a nonmagnetic layer on the first interfacial magnetic layer, a second interfacial magnetic layer on the nonmagnetic layer, a second diffusion prevention layer on the second interfacial magnetic layer, a second magnetic layer on the second diffusion prevention layer, and an upper electrode layer on the second magnetic layer. The ratio of a crystal-oriented part to the other part in the second interfacial magnetic layer is higher than the ratio of a crystal-oriented part to the other part in the first interfacial magnetic layer.
    Type: Application
    Filed: March 20, 2012
    Publication date: January 3, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji Yamakawa, Katsuaki Natori, Daisuke Ikeno, Tadashi Kai
  • Publication number: 20130005148
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a pillar on a base layer, forming a insulating layer on the base layer to cover the pillar by using GCIB method, where a lowermost portion of an upper surface of the insulating layer is lower than an upper surface of the pillar, and polishing the insulating layer and the pillar to expose a head of the pillar by using CMP method, where an end point of the polishing is the lowermost portion of the upper surface of the insulating layer.
    Type: Application
    Filed: March 23, 2012
    Publication date: January 3, 2013
    Inventors: Yasuyuki Sonoda, Kyoichi Suguro, Masatoshi Yoshikawa, Koji Yamakawa, Katsuaki Natori, Daisuke Ikeno
  • Publication number: 20120326251
    Abstract: According to one embodiment, a semiconductor memory device includes plural magneto-resistance elements being two-dimensionally arrayed on a semiconductor substrate. In the semiconductor memory device, each of the magneto-resistance elements includes: a first magnetic layer formed on the semiconductor substrate; a non-magnetic layer formed on the first magnetic layer; and a second magnetic layer formed on the non-magnetic layer, and an insulating film buried between the magneto-resistance elements adjacent to each other, a powder made of a metallic material or a magnetic material being dispersed in the insulating film.
    Type: Application
    Filed: March 20, 2012
    Publication date: December 27, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji Yamakawa, Daisuke Ikeno, Yasuyuki Sonoda
  • Publication number: 20120326252
    Abstract: According to one embodiment, a semiconductor memory device includes plural magneto-resistance elements. In the semiconductor memory device, each of the magneto-resistance elements includes: a first magnetic layer formed on a semiconductor substrate, the first magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; a non-magnetic layer formed on the first magnetic layer; a second magnetic layer formed on the non-magnetic layer, the second magnetic layer having an easy axis of magnetization perpendicular to a film surface thereof; and a sidewall film provided so as to cover a sidewall of each of the magneto-resistance elements with a protective film interposed therebetween, the sidewall film providing a tensile stress to the magneto-resistance element along the easy axis of magnetization.
    Type: Application
    Filed: March 20, 2012
    Publication date: December 27, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji Yamakawa, Katsuaki Natori, Daisuke Ikeno, Yasuyuki Sonoda
  • Publication number: 20120241879
    Abstract: According to one embodiment, a semiconductor device, includes a magneto resistive element including a first magnetic layer, a first interface magnetic layer, a nonmagnetic layer, a second interface magnetic layer and a second magnetic layer as a stacked structure in order; and a metal layer including first metal atoms, second metal atoms and boron atoms, the metal layer being provided at least one region selected from under the first magnetic, between the first magnetic layer and the first interface magnetic layer, between the second interface magnetic layer and the second magnetic layer, and upper the second magnetic layer.
    Type: Application
    Filed: September 16, 2011
    Publication date: September 27, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daisuke IKENO, Koji Yamakawa, Katsuaki Natori, Yasuyuki Sonoda
  • Publication number: 20120217476
    Abstract: According to one embodiment, a memory device with magnetroresistive effect element is disclosed. The element includes first metal magnetic film (MMF) with nonmagnetic element and axis of easy magnetization perpendicular (EMP), first insulating film, first intermediate magnetic film between the first MMF and the first insulating film, second MMF on the first insulating film and including nonmagnetic elements, the second MMF having axis of EMP, second intermediate magnetic film between the first insulating film and the second MMF, and diffusion preventing film including metal nitride having barrier property against diffusion of the nonmagnetic elements between the first MMF and the first intermediate magnetic film.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 30, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Ikeno, Koji Yamakawa, Katsuaki Natori, Yasuyuki Sonoda
  • Publication number: 20120112297
    Abstract: According to one embodiment, a magnetic random access memory including a magneto resistive element, including a free layer including first metal atoms, a first metal layer on the free layer and including a first metal, a first interfacial magnetic layer on the first metal layer, a nonmagnetic layer provided on the first interfacial magnetic layer, a second interfacial magnetic layer on the nonmagnetic layer, a second metal layer on the second interfacial magnetic layer and including a second metal, and a pinned layer provided on the second metal layer and including the second metal atoms.
    Type: Application
    Filed: March 16, 2011
    Publication date: May 10, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koji YAMAKAWA, Katsuaki NATORI, Daisuke IKENO, Yasuyuki SONODA
  • Publication number: 20120007196
    Abstract: According to one embodiment, a magnetoresistive random access memory includes a magnetoresistive element in a memory cell, the magnetoresistive element including a first metal magnetic layer, a second metal magnetic layer, and an insulation layer interposed between the first and second metal magnetic layers. An area of each of the first and second metal magnetic layers is smaller than an area of the insulation layer.
    Type: Application
    Filed: March 18, 2011
    Publication date: January 12, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuaki NATORI, Koji YAMAKAWA, Daisuke IKENO
  • Patent number: 8062950
    Abstract: A semiconductor device has a semiconductor substrate, and a capacitor which is provided on the upper side of the semiconductor substrate and composed of a lower electrode, an upper electrode and a dielectric film, the dielectric film being placed in between the lower electrode and the upper electrode, the lower electrode including a noble metal film, and a plurality of conductive oxide films formed in an islands arrangement on the noble metal film.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: November 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Yamakawa, Soichi Yamazaki
  • Patent number: 8010022
    Abstract: A developing roller having a properly adjusted toner feed quantity comprises a shaft, an elastic layer and a surface covering layer, in which a JIS 10-point average roughness (Rz) of the surface is 4-7 ?m and a specular gloss at 85° according to JIS Z8741 of the surface is 14-55.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: August 30, 2011
    Assignee: Bridgestone Corporation
    Inventor: Koji Yamakawa
  • Publication number: 20110140238
    Abstract: According to an embodiment, there is provided a method for manufacturing a semiconductor device having a ferroelectric capacitor including a lower electrode, an upper electrode, and a dielectric film provided between the lower electrode and the upper electrode. The method includes firstly forming a conductive film on the lower electrode. Next, it includes forming an SRO film on the conductive film. Then, it includes performing a first thermal treatment crystallizing the SRO film. Then, it includes forming a first PZT film on the SRO film by the sputtering method and performing a second thermal treatment crystallizing the first PZT film. Then, it includes forming the second PZT film on the first PZT film by the CVD method.
    Type: Application
    Filed: September 21, 2010
    Publication date: June 16, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuaki NATORI, Koji YAMAKAWA, Takayuki OKADA, Iwao KUNISHIMA, Hiroshi NAKAKI
  • Publication number: 20100330769
    Abstract: A semiconductor device has a semiconductor substrate, and a capacitor which is provided on the upper side of the semiconductor substrate and composed of a lower electrode, an upper electrode and a dielectric film, the dielectric film being placed in between the lower electrode and the upper electrode, the lower electrode including a noble metal film, and a plurality of conductive oxide films formed in an islands arrangement on the noble metal film.
    Type: Application
    Filed: September 2, 2010
    Publication date: December 30, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koji Yamakawa, Soichi Yamazaki
  • Patent number: 7812425
    Abstract: A semiconductor device has a semiconductor substrate, and a capacitor which is provided on the upper side of the semiconductor substrate and composed of a lower electrode, an upper electrode and a dielectric film, the dielectric film being placed in between the lower electrode and the upper electrode, the lower electrode including a noble metal film, and a plurality of conductive oxide films formed in an islands arrangement on the noble metal film.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: October 12, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Yamakawa, Soichi Yamazaki
  • Patent number: 7728368
    Abstract: According to an aspect of the invention, there is provided a semiconductor device including a semiconductor substrate, a lower electrode film formed on the semiconductor substrate, a dielectric film formed on the lower electrode film, and an upper electrode film formed on the dielectric film, wherein the lower electrode film, the dielectric film and the upper electrode film construct a capacitor in a predetermined region on the semiconductor substrate, the dielectric film is separated from the upper electrode film outside the predetermined region, and the dielectric film is formed continuously with respect to an adjacent cell.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: June 1, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Soichi Yamazaki, Koji Yamakawa