Patents by Inventor Koji Yamakawa

Koji Yamakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7259094
    Abstract: An apparatus for manufacturing a semiconductor device is disclosed which comprises a chamber which holds a to-be-processed substrate having a film containing at least one kind of metal element which will become a component of a volatile metal compound, a heater which heats the substrate held in the chamber, and an adsorbent which is provided in the chamber and which adsorbs the volatile metal compound generated from the film by heating the substrate.
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: August 21, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Keisuke Nakazawa, Koji Yamakawa, Hiroyuki Kanaya, Yoshinori Kumura, Hiroshi Itokawa, Osamu Arisumi
  • Patent number: 7233040
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, and a capacitor provided above the semiconductor substrate and including a film which contains Pb, Sr, Zr, Ti, Ru and O and a dielectric film which contains Pb, Zr, Ti and O and which is provided on the film containing Pb, Sr, Zr, Ti, Ru and O.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: June 19, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keisuke Nakazawa, Koji Yamakawa, Katsuaki Natori, Soichi Yamazaki, Hiroshi Itokawa, Hiroyuki Kanaya
  • Publication number: 20070126338
    Abstract: A PED is constituted by arranging signal lines and scanning lines, in the form of a matrix, on the inner surface of a rear substrate and by forming PZT films, which are used as electron-emitting members, at the intersections of the signal lines and the scanning lines. When a voltage is applied between element electrodes connected to the lines, each PZT film emits an electron beam having a cross-section shape that depends on the shape of the PZT film.
    Type: Application
    Filed: February 5, 2007
    Publication date: June 7, 2007
    Inventors: Kaoru KOIWA, Koji Yamakawa
  • Publication number: 20070111334
    Abstract: A semiconductor device according to the present invention comprises a semiconductor substrate, a capacitor including a lower electrode disposed above the semiconductor substrate, a dielectric film disposed above the lower electrode, and an upper electrode disposed above the dielectric film, the upper electrode including metal oxide formed of ABO.sub.3 perovskite oxide and containing at least an Ru element as a B site element, and a metal film containing a Ti element being disposed between the dielectric film and the upper electrode.
    Type: Application
    Filed: December 27, 2006
    Publication date: May 17, 2007
    Applicants: KABUSHHIKI KAISHA TOSHIBA, INFINEON TECNOLOGIES AG
    Inventors: Hiroshi ITOKAWA, Koji Yamakawa, Rainer Bruchhaus
  • Publication number: 20070096180
    Abstract: A semiconductor device includes a semiconductor substrate, and a ferroelectric capacitor provided on the semiconductor substrate, the ferroelectric capacitor comprising a lower electrode, a first ferroelectric film provided on the lower electrode including Pb(ZrxTi1-x)O3 and having a tetragonal crystal system whose crystal direction is oriented in a <111> direction, a second ferroelectric film provided on the first ferroelectric film including Pb(ZryTi1-y)O3 and having a tetragonal crystal system whose crystal direction is oriented in the <111> direction, and an upper electrode provided on the second ferroelectric film.
    Type: Application
    Filed: September 21, 2006
    Publication date: May 3, 2007
    Inventors: Koji Yamakawa, Soichi Yamazaki, Osamu Hidaka, Osamu Arisumi
  • Publication number: 20070080383
    Abstract: A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate; a ferroelectric capacitor arranged above the semiconductor substrate; an insulating protecting film covering a side surface of the ferroelectric capacitor; and a side wall film formed on a side surface of the ferroelectric capacitor through the protecting film and giving tensile stress to the ferroelectric capacitor in a direction of an electric field applied to the ferroelectric capacitor.
    Type: Application
    Filed: July 10, 2006
    Publication date: April 12, 2007
    Inventors: Koji Yamakawa, Soichi Yamazaki
  • Patent number: 7190015
    Abstract: A semiconductor device including a semiconductor substrate, a capacitor formed above the semiconductor substrate, a first interlayer insulating film formed above the capacitor and having a trench, a wiring formed above the capacitor and formed in the trench, the wiring have a top surface flush with a top surface of the first interlayer insulating film, a first hydrogen barrier film formed in contact with the top surface of the wiring and the top surface of the first interlayer insulating film and preventing hydrogen from diffusing into the capacitor and a second interlayer insulating film formed on the first hydrogen barrier film.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: March 13, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Koji Yamakawa, Hiroyuki Kanaya
  • Patent number: 7151288
    Abstract: A semiconductor device comprises a semiconductor substrate, a conductive plug electrically connected to the semiconductor substrate, a silicon carbide film provided on the conductive plug, a metal compound film provided on the silicon carbide film and containing a metal carbide, and an electrode provided on the metal compound film.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: December 19, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keitaro Imai, Koji Yamakawa
  • Publication number: 20060244022
    Abstract: According to an aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate, a capacitor which is disposed above the semiconductor substrate and in which a dielectric film is held between lower and upper electrodes, an oxide film formed in such a manner as to coat the capacitor and having a thickness of 5 nm or more and 50 nm or less, and a protective film formed on the oxide film by an ALD process.
    Type: Application
    Filed: June 30, 2005
    Publication date: November 2, 2006
    Inventors: Katsuaki Natori, Hiroyuki Kanaya, Koji Yamakawa
  • Publication number: 20060234442
    Abstract: According to an aspect of the invention, there is provided a semiconductor device comprising a capacitor formed above a semiconductor substrate by sandwiching a dielectric film between a lower electrode and an upper electrode including an electrode film which contains an MOx type conductive oxide (M is a metal element, O is an oxygen element, and x>0), and a contact connected to the upper electrode, wherein a film thickness of the electrode film immediately below the contact is smaller than a film thickness of the electrode film in the other portion.
    Type: Application
    Filed: April 14, 2006
    Publication date: October 19, 2006
    Inventors: Soichi Yamazaki, Koji Yamakawa
  • Publication number: 20060231880
    Abstract: According to an aspect of the invention, there is provided a semiconductor device including a semiconductor substrate, and a capacitor formed above the semiconductor substrate by sandwiching a dielectric film between a lower electrode and upper electrode, wherein the upper electrode has a stacked structure including a first MOx type conductive oxide film (M is a metal element, O is an oxygen element, and x>0) having a crystal structure, and a crystal grain size of the first MOx type conductive oxide film is 5 to 100 nm.
    Type: Application
    Filed: April 7, 2006
    Publication date: October 19, 2006
    Inventors: Koji Yamakawa, Soichi Yamazaki, Osamu Hidaka
  • Patent number: 7122851
    Abstract: A semiconductor device comprising a semiconductor substrate, and a capacitor provided above the semiconductor substrate, and including a bottom electrode, a top electrode and a dielectric film between the bottom and top electrodes, the bottom electrode including a conductive film selected from a noble metal film and a noble metal oxide film, a metal oxide film having a perovskite structure, provided between the dielectric film and the conductive film, expressed by ABO3, and containing first metal element as B-site element, and a metal film provided between the conductive film and the metal oxide film, and containing second metal element which is B-site element of a metal oxide having a perovskite structure, a decrease of Gibbs free energy when the second metal element forms oxide being larger than that when the first metal element forms oxide, a thickness of the metal oxide film being 5 nm or less.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: October 17, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Itokawa, Koji Yamakawa, Katsuaki Natori
  • Publication number: 20060214210
    Abstract: A semiconductor device according to an aspect of the invention comprises a semiconductor substrate, a conductive plug which is connected to an active region of a transistor formed on the semiconductor substrate, a metal silicide film which covers a bottom surface portion and side surface portion of the conductive plug, and an electrode structure which is formed on the conductive plug.
    Type: Application
    Filed: April 4, 2005
    Publication date: September 28, 2006
    Inventors: Hiroshi Itokawa, Keitaro Imai, Koji Yamakawa, Bum-ki Moon
  • Patent number: 7105400
    Abstract: There is disclosed a method of manufacturing a semiconductor device, comprising forming an underlying region including an interlevel insulating film on a semiconductor substrate, forming an alumina film on the underlying region, forming a hole in the alumina film, filling the hole with a bottom electrode film, forming a dielectric film on the bottom electrode film, and forming a top electrode film on the dielectric film.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: September 12, 2006
    Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies, AG
    Inventors: Keitaro Imai, Koji Yamakawa, Hiroshi Itokawa, Katsuaki Natori, Osamu Arisumi, Keisuke Nakazawa, Bum-ki Moon
  • Patent number: 7091538
    Abstract: A semiconductor device comprises a semiconductor substrate including a diffusion area, a capacitor provided above the semiconductor substrate and including a lower electrode, a dielectric film, and an upper electrode, a plug provided between the semiconductor substrate and the capacitor and having a lower end connected to the diffusion area and an upper end connected to the lower electrode, and a dummy plug provided between the semiconductor substrate and the capacitor and having a lower end not connected to the diffusion area and an upper end connected to the lower electrode.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: August 15, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Natori, Koji Yamakawa, Hiroyuki Kanaya
  • Publication number: 20060108624
    Abstract: A semiconductor device comprises a capacitor including a bottom electrode, a top electrode, and a dielectric film, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a conductive metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film, the dielectric film including an insulating metal oxide film having a perovskite structure, the insulating metal oxide film being expressed by A(ZrxTi1-x)O3 (A is at least one A site element, 0<x<0.35).
    Type: Application
    Filed: December 30, 2004
    Publication date: May 25, 2006
    Inventors: Hiroshi Itokawa, Koji Yamakawa
  • Patent number: 7049650
    Abstract: A semiconductor device comprises a capacitor including a bottom electrode, a top electrode, and a dielectric film, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a conductive metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film, the dielectric film including an insulating metal oxide film having a perovskite structure, the insulating metal oxide film being expressed by A(ZrxTi1-x)O3 (A is at least one A site element, 0<x<0.35).
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: May 23, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Itokawa, Koji Yamakawa
  • Publication number: 20060102941
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film.
    Type: Application
    Filed: November 12, 2004
    Publication date: May 18, 2006
    Inventors: Hiroshi Itokawa, Koji Yamakawa, Tohru Ozaki, Yoshinori Kumura, Takamichi Tsuchiya, Nicolas Nagel, Bum-Ki Moon, Andreas Hilliger
  • Patent number: 7042037
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a top electrode, and a dielectric film provided between the bottom electrode and the top electrode, the bottom electrode comprising a first conductive film containing iridium, a second conductive film provided between the dielectric film and the first conductive film and formed of a noble metal film, a third conductive film provided between the dielectric film and the second conductive film and formed of a metal oxide film having a perovskite structure, and a diffusion prevention film provided between the first conductive film and the second conductive film and including at least one of a metal film and a metal oxide film, the diffusion prevention film preventing diffusion of iridium contained in the first conductive film.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: May 9, 2006
    Assignees: Kabushiki Kaisha Toshiba, Infineon Technologies AG
    Inventors: Hiroshi Itokawa, Koji Yamakawa, Tohru Ozaki, Yoshinori Kumura, Takamichi Tsuchiya, Nicolas Nagel, Bum-Ki Moon, Andreas Hilliger
  • Patent number: 7009230
    Abstract: An improved barrier stack for inhibiting diffusion of atoms or molecules, such as O2 is disclosed. The barrier stack is particularly useful in capacitor over plug structures to prevent plug oxidation which can adversely impact the reliability of the structures. The barrier stack includes first and second barrier layers. In one embodiment, the first barrier layer comprises first and second sub-barrier layers having mismatched grain boundaries. The sub-barrier layers are selected from, for example, Ir, Ru, Pd, Rh, or alloys thereof. By providing mismatched grain boundaries, the interface of the sub-barrier layers block the diffusion path of oxygen. To further enhance the barrier properties, the first barrier layer is passivated with O2 using, for example, a rapid thermal oxidation. The RTO forms a thin oxide layer on the surface of the first barrier layer. The oxide layer can advantageously promote mismatching of the grain boundaries of the first and second sub-barrier layer.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: March 7, 2006
    Assignees: Infineon Technologies Aktiengesellschaft, Kabushiki Kaisha Toshiba
    Inventors: Bum Ki Moon, Gerhard Beitel, Nicolas Nagel, Andreas Hilliger, Koji Yamakawa, Keitaro Imai