Patents by Inventor Krishnaswamy Ramkumar
Krishnaswamy Ramkumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190198329Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.Type: ApplicationFiled: January 4, 2019Publication date: June 27, 2019Applicant: Cypress Semiconductor CorporationInventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
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Patent number: 10332599Abstract: A memory device that includes a non-volatile memory (NVM) array, divided into a flash memory portion and an electrically erasable programmable read-only memory (EEPROM) portion. The NVM array includes charge-trapping memory cells arranged in rows and columns, in which each memory cell has a memory transistor including an angled lightly doped drain (LDD) implant, and a select transistor including a shared source region with a halo implant. The flash memory portion and the EEPROM portion are disposed within one single semiconductor die. Other embodiments are also disclosed.Type: GrantFiled: March 12, 2018Date of Patent: June 25, 2019Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.Inventors: Gary Menezes, Krishnaswamy Ramkumar, Ali Keshavarzi, Venkatraman Prabhakar
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Patent number: 10319733Abstract: A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the plasma oxidation. The memory transistor further includes a tunneling layer disposed beneath the multi-layer charge storage layer and a channel region disposed beneath the tunneling layer, where the channel region is positioned laterally between a source region and a drain region.Type: GrantFiled: September 19, 2018Date of Patent: June 11, 2019Assignee: Cypress Semiconductor CorporationInventors: Jeong Soo Byun, Krishnaswamy Ramkumar
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Patent number: 10312336Abstract: Semiconductor devices including non-volatile memory devices and methods of fabricating the same are provided. Generally, the memory device includes a gate structure, a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. In one embodiment, the multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide, and the first and the second dielectric layers include a nitride. Other embodiments are also disclosed.Type: GrantFiled: January 8, 2018Date of Patent: June 4, 2019Assignee: Cypress Semiconductor CorporationInventors: Igor Polishchuk, Sagy Charel Levy, Krishnaswamy Ramkumar
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Patent number: 10304968Abstract: A memory device is described. Generally, the memory device includes a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in a substrate, a multi-layer charge storing layer overlying the tunnel oxide layer and a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The multi-layer charge storing layer includes an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a composition of the first layer results in it being substantially trap free, and an oxygen-lean, second layer comprising a nitride on the first layer in which a composition of the second layer results in it being trap dense. The HTO layer includes an oxidized portion of the second layer. Other embodiments are also described.Type: GrantFiled: January 26, 2015Date of Patent: May 28, 2019Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Sagy Charel Levy, Jeong Soo Byun
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Publication number: 20190157286Abstract: A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.Type: ApplicationFiled: November 13, 2018Publication date: May 23, 2019Applicant: Cypress Semiconductor CorporationInventor: Krishnaswamy Ramkumar
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Publication number: 20190147960Abstract: A memory device that includes a non-volatile memory (NVM) array, divided into a flash memory portion and an electrically erasable programmable read-only memory (EEPROM) portion. The NVM array includes charge-trapping memory cells arranged in rows and columns, in which each memory cell has a memory transistor including an angled lightly doped drain (LDD) implant, and a select transistor including a shared source region with a halo implant. The flash memory portion and the EEPROM portion are disposed within one single semiconductor die. Other embodiments are also disclosed.Type: ApplicationFiled: March 12, 2018Publication date: May 16, 2019Applicant: Cypress Semiconductor CorporationInventors: Gary Menezes, Krishnaswamy Ramkumar, Ali Keshavarzi, Venkatraman Prabhakar
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Patent number: 10269985Abstract: A memory device is described. Generally, the memory device includes a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in a substrate, a multi-layer charge storing layer overlying the tunnel oxide layer and a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The multi-layer charge storing layer includes an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a composition of the first layer results in it being substantially trap free, and an oxygen-lean, second layer comprising a nitride on the first layer in which a composition of the second layer results in it being trap dense. The HTO layer includes an oxidized portion of the second layer. Other embodiments are also described.Type: GrantFiled: January 26, 2015Date of Patent: April 23, 2019Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Sagy Charel Levy, Jeong Soo Byun
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Patent number: 10263087Abstract: A memory is described. Generally, the memory includes a number of non-planar multigate transistors, each including a channel of semiconducting material overlying a surface of a substrate and electrically connecting a source and a drain, a tunnel dielectric layer overlying the channel on at least three sides thereof, and a multi-layer charge-trapping region overlying the tunnel dielectric layer. In one embodiment, the multi-layer charge-trapping region includes a first deuterated layer overlying the tunnel dielectric layer and a first nitride-containing layer overlying the first deuterated layer. Other embodiments are also described.Type: GrantFiled: July 18, 2017Date of Patent: April 16, 2019Assignee: Cypress Semiconductor CorporationInventors: Sagy Levy, Fredrick Jenne, Krishnaswamy Ramkumar
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Publication number: 20190103414Abstract: Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a non-volatile memory (NVM) transistor including a charge-trapping layer and a blocking dielectric, a field-effect transistor (FET) of a first type including a first gate dielectric having a first thickness, a FET of a second type including a second gate dielectric having a second thickness, and a FET of a third type including a third gate dielectric having a third thickness. In some embodiments, the first, second, and third gate dielectric includes a high dielectric constant (high-K) dielectric layer, and the first thickness is greater than the second thickness, the second thickness is greater than the third thickness. Other embodiments are also described.Type: ApplicationFiled: November 21, 2017Publication date: April 4, 2019Applicant: Cypress Semiconductor CorporationInventor: Krishnaswamy Ramkumar
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Publication number: 20190088487Abstract: A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.Type: ApplicationFiled: August 8, 2018Publication date: March 21, 2019Applicant: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Igor Kouznetsov, Venkatraman Prabhakar, Ali Keshavarzi
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Publication number: 20190088669Abstract: A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the plasma oxidation. The memory transistor further includes a tunneling layer disposed beneath the multi-layer charge storage layer and a channel region disposed beneath the tunneling layer, where the channel region is positioned laterally between a source region and a drain region.Type: ApplicationFiled: September 19, 2018Publication date: March 21, 2019Applicant: Cypress Semiconductor CorporationInventors: Jeong Soo Byun, Krishnaswamy Ramkumar
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Publication number: 20190067313Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.Type: ApplicationFiled: July 24, 2018Publication date: February 28, 2019Applicant: Cypress Semiconductor CorporationInventor: Krishnaswamy Ramkumar
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Patent number: 10199229Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.Type: GrantFiled: July 28, 2017Date of Patent: February 5, 2019Assignee: Cypress Semiconductor CorporationInventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
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Publication number: 20180366564Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.Type: ApplicationFiled: May 30, 2018Publication date: December 20, 2018Applicant: Cypress Semiconductor CorporationInventors: Sagy Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam Geha
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Publication number: 20180366563Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.Type: ApplicationFiled: May 30, 2018Publication date: December 20, 2018Applicant: Cypress Semiconductor CorporationInventors: Sagy Levy, Krishnaswamy Ramkumar, Fredrick Jenne, Sam Geha
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Patent number: 10153294Abstract: A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.Type: GrantFiled: September 29, 2017Date of Patent: December 11, 2018Assignee: Cypress Semiconductor CorporationInventor: Krishnaswamy Ramkumar
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Publication number: 20180351004Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.Type: ApplicationFiled: June 5, 2018Publication date: December 6, 2018Applicant: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Sagy Charel Levy, Jeong Soo Byun
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Publication number: 20180351003Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.Type: ApplicationFiled: May 24, 2018Publication date: December 6, 2018Applicant: Cypress Semiconductor CorporationInventors: Fredrick B. Jenne, Sagy Charel Levy, Krishnaswamy Ramkumar
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Patent number: 10128258Abstract: A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the plasm oxidation. The memory transistor further includes a tunneling layer disposed beneath the multi-layer charge storage layer and a channel region disposed beneath the tunneling layer, where the channel region is positioned laterally between a source region and a drain region.Type: GrantFiled: September 15, 2016Date of Patent: November 13, 2018Assignee: Cypress Semiconductor CorporationInventors: Jeong Soo Byun, Krishnaswamy Ramkumar