Abstract: A memory device is described. Generally, the memory device includes a tunnel oxide layer overlying a channel connecting a source and a drain of the memory device formed in a substrate, a multi-layer charge storing layer overlying the tunnel oxide layer and a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The multi-layer charge storing layer includes an oxygen-rich, first layer comprising a nitride on the tunnel oxide layer in which a composition of the first layer results in it being substantially trap free, and an oxygen-lean, second layer comprising a nitride on the first layer in which a composition of the second layer results in it being trap dense. The HTO layer includes an oxidized portion of the second layer. Other embodiments are also described.

Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.

Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region. A gate stack is disposed above the substrate over the channel region. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

Abstract: A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.

Abstract: A 3-D/vertical non-volatile (NV) memory device such as 3-D NAND flash memory and fabrication method thereof, the NV memory device includes vertical openings disposed in a stack of alternating stack layers of first stack layers and second stack layers over a wafer, a multi-layer dielectric disposed over an inner sidewall of each opening, a first channel layer disposed over the multi-layer dielectric, and a second channel layer disposed over the first channel layer, in which at least one of the first or second channel layers includes polycrystalline germanium or silicon-germanium.

Abstract: Methods of integrating complementary SONOS devices into a CMOS process flow are described. The method begins with depositing and patterning a first photoresist mask over a surface of a substrate to expose a N-SONOS region, and implanting a channel for a NSONOS device through a first pad oxide, followed by depositing and patterning a second photoresist mask to expose a P-SONOS region, and implanting a channel for a PSONOS device through a second pad oxide. Next, a number of Nwells are concurrently implanted for the PSONOS device and a PMOS device in a core region of the substrate. Finally, the first and second pad oxides, which were left in place to separate the P-SONOS region and the N-SONOS region from the first and second photoresist masks, are concurrently removed. In one embodiment, implanting the Nwells includes implanting a single, contiguous deep Nwell for the PSONOS and PMOS device.

Abstract: A memory device that includes a non-volatile memory (NVM) transistor disposed in a first region of a substrate. The NVM transistor includes a first gate including a first type of conductor material. The memory device further includes a first type of low voltage field-effect transistor (LV FET) and an input/out field-effect transistor (I/O FET) disposed in a second region of the substrate. The LV FET includes a second gate comprising a second type of conductor material, the I/O FET includes a third gate comprising a second type of conductor material, and the first and second conductor materials are different. Other embodiments are also described.

Abstract: Methods of integrating complementary SONOS devices into a CMOS process flow are described. In one embodiment, the method begins with depositing a hardmask (HM) over a substrate including a first-SONOS region and a second-SONOS region. A first tunnel mask (TUNM) is formed over the HM exposing a first portion of the HM in the second-SONOS region. The first portion of the HM is etched, a channel for a first SONOS device implanted through a first pad oxide overlying the second-SONOS region and the first TUNM removed. A second TUNM is formed exposing a second portion of the HM in the first-SONOS region. The second portion of the HM is etched, a channel for a second SONOS device implanted through a second pad oxide overlying the first-SONOS region and the second TUNM removed. The first and second pad oxides are concurrently etched, and the HM removed.

Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

Abstract: Semiconductor devices including non-volatile memory devices and methods of fabricating the same are provided. Generally, the memory device includes a gate structure, a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. In one embodiment, the multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide, and the first and the second dielectric layers include a nitride. Other embodiments are also disclosed.

Abstract: An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.

Abstract: A method of controlling the thickness of gate oxides in an integrated CMOS process which includes performing a two-step gate oxidation process to concurrently oxidize and therefore consume at least a first portion of the cap layer of the NV gate stack to form a blocking oxide and form a gate oxide of at least one metal-oxide-semiconductor (MOS) transistor in the second region, wherein the gate oxide of the at least one MOS transistor is formed during both a first oxidation step and a second oxidation step of the gate oxidation process.

Abstract: Memory devices and methods for forming the same are disclosed. In one embodiment, the device includes a non-volatile memory (NVM) transistor formed in a first region of a substrate, the NVM transistor comprising a channel and a gate stack on the substrate overlying the channel. The gate stack includes a dielectric layer on the substrate, a charge-trapping layer on the dielectric layer, an oxide layer overlying the charge-trapping layer, a first gate overlying the oxide layer, and a first silicide region overlying the first gate. The device includes a metal-oxide-semiconductor transistor formed in a second region of the substrate comprising a gate oxide overlying the substrate in the second region, a second gate overlying the gate oxide, and second silicide region overlying the second gate. A strain inducing structure overlies at least the NVM transistor and a surface of the substrate in the first region of the substrate.

Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors are described. The memory cell includes a substrate having a non-volatile memory (NVM) region and a plurality of metal-oxide-semiconductor (MOS) regions. A NVM transistor in the NVM region includes a tunnel dielectric on the substrate, a charge-trapping layer on the tunnel dielectric, and a blocking dielectric comprising a high-k dielectric material over the charge-trapping layer. The plurality of MOS regions include a number of MOS transistors. At least one of the MOS transistors includes a gate dielectric comprising a high-k dielectric material over a surface of the substrate. Generally, the blocking dielectric and the gate dielectric comprise the same high-k dielectric material. Other embodiments are also described.

Abstract: A method of fabricating a memory device is described. Generally, the method includes forming a channel from a semiconducting material overlying a surface of a substrate, and forming dielectric stack on the channel. A first cap layer is formed over the dielectric stack, and a second cap layer including a nitride formed over the first cap layer. The first and second cap layers and the dielectric stack are then patterned to form a gate stack of a device. The second cap layer is removed and an oxidation process performed to form a blocking oxide over the dielectric stack, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.

Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.

Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, method includes forming a first oxide layer over a substrate, forming a silicon-rich, oxygen-rich, oxynitride layer on the first oxide layer, forming a silicon-rich, nitrogen-rich, and oxygen-lean nitride layer over the oxynitride layer, and forming a second oxide layer on the nitride layer. Generally, the nitride layer includes a majority of charge traps distributed in the oxynitride layer and the nitride layer. Optionally, the method further includes forming a middle oxide layer between the oxynitride layer and the nitride layer. Other embodiments are also described.

Abstract: An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.

Abstract: A method of forming a transistor is described. In one embodiment the method includes: forming a channel of a transistor in a surface of a substrate; forming a dielectric stack including a first oxide layer overlying the surface of the substrate, a middle layer comprising nitride overlying the first oxide layer and a second oxide layer overlying the middle layer; forming over the dielectric stack a mask exposing source and drain (S/D) regions of the transistor; etching the dielectric stack through the mask to thin the dielectric stack by removing the second oxide layer and at least a first portion of the middle layer in S/D regions of the transistor; and implanting dopants into S/D regions of the transistor through the thinned dielectric stack to form a lightly-doped drain (LDD) adjacent to the channel of the transistor. Other embodiments are also described.

Abstract: Methods of integrating complementary SONOS devices into a CMOS process flow are described. The method begins with depositing and patterning a first photoresist mask over a surface of a substrate to expose a N-SONOS region, and implanting a channel for a NSONOS device through a first pad oxide, followed by depositing and patterning a second photoresist mask to expose a P-SONOS region, and implanting a channel for a PSONOS device through a second pad oxide. Next, a number of Nwells are concurrently implanted for the PSONOS device and a PMOS device in a core region of the substrate. Finally, the first and second pad oxides, which were left in place to separate the P-SONOS region and the N-SONOS region from the first and second photoresist masks, are concurrently removed. In one embodiment, implanting the Nwells includes implanting a single, contiguous deep Nwell for the PSONOS and PMOS device.